[all-commits] [llvm/llvm-project] 90d2f8: [mlir][vector] Teach `TransferOptimization` to loo...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90d2f8c630e1ddddd034e4a0e575929c08dd26bf
      https://github.com/llvm/llvm-project/commit/90d2f8c630e1ddddd034e4a0e575929c08dd26bf
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-05-16 (Thu, 16 May 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
    M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
    M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
    M mlir/test/Dialect/Vector/vector-transferop-opt.mlir

  Log Message:
  -----------
  [mlir][vector] Teach `TransferOptimization` to look through trivial aliases (#87805)

This allows `TransferOptimization` to eliminate and forward stores that
are to trivial aliases (rather than just to identical memref values).

A trivial aliases is (currently) defined as:

  1. A `memref.cast`
  2. A `memref.subview` with a zero offset and unit strides
  3. A chain of 1 and 2



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