[all-commits] [llvm/llvm-project] 1dd0d3: [AArch64][GISel] Fold COPY(y:gpr, DUP(x:fpr, i)) -...

[Dhruv Chawla via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae
      https://github.com/llvm/llvm-project/commit/1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae
  Author: Dhruv Chawla <dhruvc at nvidia.com>
  Date:   2024-05-16 (Thu, 16 May 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
    M llvm/test/CodeGen/AArch64/aarch64-mulv.ll
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
    M llvm/test/CodeGen/AArch64/bitcast.ll
    M llvm/test/CodeGen/AArch64/insertextract.ll
    M llvm/test/CodeGen/AArch64/ptradd.ll
    M llvm/test/CodeGen/AArch64/reduce-and.ll
    M llvm/test/CodeGen/AArch64/reduce-or.ll
    M llvm/test/CodeGen/AArch64/reduce-xor.ll

  Log Message:
  -----------
  [AArch64][GISel] Fold COPY(y:gpr, DUP(x:fpr, i)) -> UMOV(y:gpr, x:fpr, i) (#89017)

This patch adds a peephole to AArch64PostSelectOptimize for codegen
that is caused by RegBankSelect limiting G_EXTRACT_VECTOR_ELT
only to FPR registers in both the input and output registers. This can
cause a generation of COPY from FPR to GPR when, for example, the
output register of the G_EXTRACT_VECTOR_ELT is used in a branch
condition.

This was noticed when looking at codegen differences between SDAG and GI
for the s1279 kernel in the TSVC benchmark.



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