[all-commits] [llvm/llvm-project] a9763d: Merge sourcelocation in CSEMIRBuilder::getDominati...
Shubham Sandeep Rastogi via All-commits
all-commits at lists.llvm.org
Wed May 15 18:16:03 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: a9763deb2f3f20d789b947ec69360c258377db6a
https://github.com/llvm/llvm-project/commit/a9763deb2f3f20d789b947ec69360c258377db6a
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-05-15 (Wed, 15 May 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
A llvm/test/DebugInfo/AArch64/merge-locations-legalizer.mir
Log Message:
-----------
Merge sourcelocation in CSEMIRBuilder::getDominatingInstrForID. (#90922)
Make sure to merge the sourcelocation of the Dominating Instruction that
is hoisted in a basic block in the CSEMIRBuilder in the legalizer pass.
If this is not done, we can have a incorrect line table entry that makes
the instruction pointer jump around.
For example the line table without this patch looks like:
```
Address Line Column File ISA Discriminator OpIndex Flags
------------------ ------ ------ ------ --- ------------- ------- -------------
0x0000000000000000 0 0 1 0 0 0 is_stmt
0x0000000000000010 11 14 1 0 0 0 is_stmt prologue_end
0x0000000000000028 12 1 1 0 0 0 is_stmt
0x000000000000002c 12 15 1 0 0 0
0x000000000000004c 12 13 1 0 0 0
0x000000000000005c 13 1 1 0 0 0 is_stmt
0x0000000000000064 12 13 1 0 0 0 is_stmt
0x000000000000007c 13 7 1 0 0 0 is_stmt
0x00000000000000c8 13 1 1 0 0 0
0x00000000000000e8 13 1 1 0 0 0 epilogue_begin
0x00000000000000f8 13 1 1 0 0 0 end_sequence
```
The line table entry for 0x000000000000005c should be 0
After this patch, the line table looks like:
```
Address Line Column File ISA Discriminator OpIndex Flags
------------------ ------ ------ ------ --- ------------- ------- -------------
0x0000000000000000 0 0 1 0 0 0 is_stmt
0x0000000000000010 11 14 1 0 0 0 is_stmt prologue_end
0x0000000000000028 12 1 1 0 0 0 is_stmt
0x000000000000002c 12 15 1 0 0 0
0x000000000000004c 12 13 1 0 0 0
0x000000000000005c 0 0 1 0 0 0
0x0000000000000064 12 13 1 0 0 0
0x000000000000007c 13 7 1 0 0 0 is_stmt
0x00000000000000c8 13 1 1 0 0 0
0x00000000000000e8 13 1 1 0 0 0 epilogue_begin
0x00000000000000f8 13 1 1 0 0 0 end_sequence
```
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