[all-commits] [llvm/llvm-project] 0647d1: [RISCV] Remove unneeded casts from int64_t to uint...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0647d1035cb208195e002b38089b82004b6f7b92
      https://github.com/llvm/llvm-project/commit/0647d1035cb208195e002b38089b82004b6f7b92
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-05-15 (Wed, 15 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

  Log Message:
  -----------
  [RISCV] Remove unneeded casts from int64_t to uint64_t in RISCVMatInt.cpp. NFC

Most of these were to avoid undefined behavior if a shift left
changed the sign of the result. I don't think its possible to change
the sign of the result here. We're shifting left by 12 after an arithmetic
right shift by more than 12. The bits we are shifting out with the left
shift are guaranteed to be sign bits.

Also use SignExtend64<32> to force upper bits to all 1s instead of an
Or. We know the value isUInt<32> && !isInt<32> which means bit 31 is set.



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