[all-commits] [llvm/llvm-project] 9d4f7f: [test][LoongArch] Add -mattr=+d option. NFC

wanglei via All-commits all-commits at lists.llvm.org
Tue May 14 05:26:21 PDT 2024 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d4f7f44b64d87d1068859906f43b7ce03a7388b
      https://github.com/llvm/llvm-project/commit/9d4f7f44b64d87d1068859906f43b7ce03a7388b
  Author: wanglei <wanglei at loongson.cn>
  Date:   2024-05-14 (Tue, 14 May 2024)

  Changed paths:
    M llvm/test/CodeGen/LoongArch/O0-pipeline.ll
    M llvm/test/CodeGen/LoongArch/addrspacecast.ll
    M llvm/test/CodeGen/LoongArch/alloca.ll
    M llvm/test/CodeGen/LoongArch/alsl.ll
    M llvm/test/CodeGen/LoongArch/analyze-branch.ll
    M llvm/test/CodeGen/LoongArch/andn-icmp.ll
    M llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/LoongArch/bitreverse.ll
    M llvm/test/CodeGen/LoongArch/block-address.ll
    M llvm/test/CodeGen/LoongArch/blockaddress-symbol.ll
    M llvm/test/CodeGen/LoongArch/bnez-beqz.ll
    M llvm/test/CodeGen/LoongArch/branch-relaxation-spill-32.ll
    M llvm/test/CodeGen/LoongArch/branch-relaxation-spill-64.ll
    M llvm/test/CodeGen/LoongArch/branch-relaxation.ll
    M llvm/test/CodeGen/LoongArch/bstrins_d.ll
    M llvm/test/CodeGen/LoongArch/bstrins_w.ll
    M llvm/test/CodeGen/LoongArch/bstrpick_d.ll
    M llvm/test/CodeGen/LoongArch/bstrpick_w.ll
    M llvm/test/CodeGen/LoongArch/bswap-bitreverse.ll
    M llvm/test/CodeGen/LoongArch/bswap.ll
    M llvm/test/CodeGen/LoongArch/bytepick.ll
    M llvm/test/CodeGen/LoongArch/code-models.ll
    M llvm/test/CodeGen/LoongArch/cpu-name-generic.ll
    M llvm/test/CodeGen/LoongArch/cpus.ll
    M llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/LoongArch/duplicate-returns-for-tailcall.ll
    M llvm/test/CodeGen/LoongArch/dwarf-eh.ll
    M llvm/test/CodeGen/LoongArch/e_flags.ll
    M llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll
    M llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll
    M llvm/test/CodeGen/LoongArch/exception-pointer-register.ll
    M llvm/test/CodeGen/LoongArch/expand-call.ll
    M llvm/test/CodeGen/LoongArch/frame.ll
    M llvm/test/CodeGen/LoongArch/frameaddr-returnaddr.ll
    M llvm/test/CodeGen/LoongArch/gep-imm.ll
    M llvm/test/CodeGen/LoongArch/get-reg-error-la32.ll
    M llvm/test/CodeGen/LoongArch/get-reg-error-la64.ll
    M llvm/test/CodeGen/LoongArch/get-reg.ll
    M llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
    M llvm/test/CodeGen/LoongArch/global-address.ll
    M llvm/test/CodeGen/LoongArch/global-variable-code-model.ll
    M llvm/test/CodeGen/LoongArch/imm.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-reg-names-error.ll
    M llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-csr-side-effects.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-iocsr-side-effects.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-memcpy.ll
    M llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/add.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/and.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/ashr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/br.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/call.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/fence-singlethread.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/fence.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/icmp.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/indirectbr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/load-store-atomic.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/lshr.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/or.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/select-bare-int.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/select-icc-int.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sext-zext-trunc.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/shl.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/sub.ll
    M llvm/test/CodeGen/LoongArch/ir-instruction/xor.ll
    M llvm/test/CodeGen/LoongArch/jump-table.ll
    M llvm/test/CodeGen/LoongArch/ldptr.ll
    M llvm/test/CodeGen/LoongArch/ldx-stx-sp-2.ll
    M llvm/test/CodeGen/LoongArch/ldx-stx-sp-3.ll
    M llvm/test/CodeGen/LoongArch/legalicmpimm.ll
    M llvm/test/CodeGen/LoongArch/load-store-offset.ll
    M llvm/test/CodeGen/LoongArch/memcmp.ll
    M llvm/test/CodeGen/LoongArch/mir-target-flags.ll
    M llvm/test/CodeGen/LoongArch/nomerge.ll
    M llvm/test/CodeGen/LoongArch/not.ll
    M llvm/test/CodeGen/LoongArch/numeric-reg-names.ll
    M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
    M llvm/test/CodeGen/LoongArch/patchable-function-entry.ll
    M llvm/test/CodeGen/LoongArch/prefer-w-inst.ll
    M llvm/test/CodeGen/LoongArch/preferred-alignments.ll
    M llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll
    M llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
    M llvm/test/CodeGen/LoongArch/returnaddr-error.ll
    M llvm/test/CodeGen/LoongArch/rotl-rotr.ll
    M llvm/test/CodeGen/LoongArch/select-const.ll
    M llvm/test/CodeGen/LoongArch/select-to-shiftand.ll
    M llvm/test/CodeGen/LoongArch/sext-cheaper-than-zext.ll
    M llvm/test/CodeGen/LoongArch/shift-masked-shamt.ll
    M llvm/test/CodeGen/LoongArch/shrinkwrap.ll
    M llvm/test/CodeGen/LoongArch/smul-with-overflow.ll
    M llvm/test/CodeGen/LoongArch/spill-ra-without-kill.ll
    M llvm/test/CodeGen/LoongArch/split-sp-adjust.ll
    M llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/LoongArch/stack-realignment.ll
    M llvm/test/CodeGen/LoongArch/stptr.ll
    M llvm/test/CodeGen/LoongArch/tail-calls.ll
    M llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
    M llvm/test/CodeGen/LoongArch/thread-pointer.ll
    M llvm/test/CodeGen/LoongArch/tls-models.ll
    M llvm/test/CodeGen/LoongArch/trap.ll
    M llvm/test/CodeGen/LoongArch/unaligned-access.ll
    M llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll
    M llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll
    M llvm/test/Transforms/AtomicExpand/LoongArch/load-store-atomic.ll
    M llvm/test/Transforms/CodeGenPrepare/LoongArch/splitgep.ll
    M llvm/test/Transforms/LoopDataPrefetch/LoongArch/basic.ll

  Log Message:
  -----------
  [test][LoongArch] Add -mattr=+d option. NFC

Because most of tests assume target-abi=`lp64d`, adding the
corresponding feature is reasonable.

rg -l loongarch -g '!*.s' | xargs sed -i '/mtriple=loongarch/ {/-mattr=/!{/target-abi/! s/mtriple=loongarch.. /&-mattr=+d /}}'



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications

More information about the All-commits mailing list