[all-commits] [llvm/llvm-project] 6140b5: [RISCV] Use RISCVISD::SHL_ADD in transformAddShlIm...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6140b5bae475069f958f90a81fb9d69c969daab6
      https://github.com/llvm/llvm-project/commit/6140b5bae475069f958f90a81fb9d69c969daab6
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-05-13 (Mon, 13 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll

  Log Message:
  -----------
  [RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm (#89832)

Doing so avoids negative interactions with other combines which don't
know the shl_add is a single instruction. From the commit log, we've had
several combine loops already.

This was originally posted as part of #88791, where a bug was pointed
out. That bug was fixed by #89789 which hits the same issue from another
angle. To confirm the fix, I included the reduced test case here.



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