[all-commits] [llvm/llvm-project] 0ebe48: [RISCV] Move RISCVInsertVSETVLI after CSR/VXRM pas...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ebe48f068c0ca69f76ed68b621c9294acd75f76
      https://github.com/llvm/llvm-project/commit/0ebe48f068c0ca69f76ed68b621c9294acd75f76
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-05-10 (Fri, 10 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/commutable.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
    M llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vxrm.mir

  Log Message:
  -----------
  [RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

This further splits off #91440 to inch RISCVInsertVSETVLI closer to post
vector regalloc.

As noted in #91440, most of the diffs are from moving vsetvli insertion
after the vxrm/csr insertion passes, but these are getting conflated
with the changes from moving to LiveIntervals.

One idea was that we could try and remove some of these diffs by
manually moving back the vsetvlis past the vxrm/csr instructions. But
this meant having to touch up the LiveIntervals again which seemed to
lead to even more diffs.

This instead just moves RISCVInsertVSETVLI after RISCVInsertReadWriteCSR
and RISCVInsertWriteVXRM so we can isolate those changes.



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