[all-commits] [llvm/llvm-project] 8296f0: [RISCV] Add invariants that registers always have ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8296f061aafb844bf3b9b002b7791ade7a1d3006
      https://github.com/llvm/llvm-project/commit/8296f061aafb844bf3b9b002b7791ade7a1d3006
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-05-08 (Wed, 08 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

  Log Message:
  -----------
  [RISCV] Add invariants that registers always have definitions. NFC (#90587)

For vector merge operands, we check if it's a NoRegister beforehand so
any other register type should have a definition.

For VL operands, they don't get replaced with NoRegisters since they're
scalar and should also always have a definition, even if it's an
implicit_def.

All the definitions at this stage should also be unique, this will
change in #70549



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