[all-commits] [llvm/llvm-project] e3f42b: [RISCV] Expand PseudoTAIL with t2 instead of t1 fo...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e3f42b02a4129947ca2dd820bfb63ffed83027b7
      https://github.com/llvm/llvm-project/commit/e3f42b02a4129947ca2dd820bfb63ffed83027b7
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2024-05-02 (Thu, 02 May 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/test/MC/RISCV/tail-call.s

  Log Message:
  -----------
  [RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp. (#89014)

PseudoTail should be a software guarded branch in Ziciflp, since its
branch target is known in link time. JALR/C.JR/C.JALR with rs1 as t2 is
termed a software guarded branch. Such branches do not need to land on a
lpad instruction.

ABI Change PR: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93



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