[all-commits] [llvm/llvm-project] 0c032f: [RISCV] Use SHL_ADD in remaining strength reduce c...
agozillon via All-commits
all-commits at lists.llvm.org
Wed May 1 10:08:11 PDT 2024
Branch: refs/heads/users/agozillon/main.openmpmlir-extend-record-member-map-support-for-omp-dialect-to-llvm-ir
Home: https://github.com/llvm/llvm-project
Commit: 0c032fd5425d853dfc577e607b9c179d811cec19
https://github.com/llvm/llvm-project/commit/0c032fd5425d853dfc577e607b9c179d811cec19
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
Log Message:
-----------
[RISCV] Use SHL_ADD in remaining strength reduce cases for MUL (#89789)
The interesting bit is the zext folding. This is the first case where we
end up with a profitable fold of shNadd (zext x), y to shNadd.uw x, y.
See zext_mul68 from rv64zba.ll.
The test differences are cases where we can legally fold (only because
there's no one use check). These are not profitable or harmful, but we
can't a oneuse check without breaking the zext_mul68 case.
Note that XTHeadBa doesn't appear to have the equivalent patterns so
this only shows up in Zba.
Commit: 2662bce43469e37c6fdabf9a77bbfbccaedf9f9f
https://github.com/llvm/llvm-project/commit/2662bce43469e37c6fdabf9a77bbfbccaedf9f9f
Author: Thurston Dang <thurston at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
A llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
Log Message:
-----------
[hwasan] Add test for hwasan pass with fixed shadow (#89813)
This test records the current behavior of HWASan, which doesn't utilize
the fixed shadow intrinsics of
https://github.com/llvm/llvm-project/commit/365bddf634993d5ea357e9715d8aacd7ee40c4b5
It is intended to be updated in future work ("Optimize outlined
memaccess for fixed shadow on Aarch64";
https://github.com/llvm/llvm-project/pull/88544)
Commit: 837dab96d6f5bece79fd58d28ea2e6f7c0912493
https://github.com/llvm/llvm-project/commit/837dab96d6f5bece79fd58d28ea2e6f7c0912493
Author: Roland McGrath <mcgrathr at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/FEnvSafeTest.cpp
A libc/test/UnitTest/FEnvSafeTest.h
M libc/test/src/fenv/CMakeLists.txt
M libc/test/src/fenv/enabled_exceptions_test.cpp
M libc/test/src/fenv/exception_flags_test.cpp
M libc/test/src/fenv/exception_status_test.cpp
A libc/test/src/fenv/excepts.h
M libc/test/src/fenv/feclearexcept_test.cpp
M libc/test/src/fenv/feenableexcept_test.cpp
M libc/test/src/fenv/feholdexcept_test.cpp
M libc/test/src/fenv/feupdateenv_test.cpp
M libc/test/src/fenv/getenv_and_setenv_test.cpp
M libc/test/src/fenv/rounding_mode_test.cpp
M libc/test/src/math/CeilTest.h
M libc/test/src/math/CopySignTest.h
M libc/test/src/math/FAbsTest.h
M libc/test/src/math/FDimTest.h
M libc/test/src/math/FMaxTest.h
M libc/test/src/math/FMinTest.h
M libc/test/src/math/FModTest.h
M libc/test/src/math/FloorTest.h
M libc/test/src/math/FmaTest.h
M libc/test/src/math/FrexpTest.h
M libc/test/src/math/HypotTest.h
M libc/test/src/math/ILogbTest.h
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/LogbTest.h
M libc/test/src/math/ModfTest.h
M libc/test/src/math/NextAfterTest.h
M libc/test/src/math/RIntTest.h
M libc/test/src/math/RemQuoTest.h
M libc/test/src/math/RoundEvenTest.h
M libc/test/src/math/RoundTest.h
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/SqrtTest.h
M libc/test/src/math/TruncTest.h
M libc/test/src/math/exhaustive/fmod_generic_impl_test.cpp
M libc/test/src/math/smoke/CanonicalizeTest.h
M libc/test/src/math/smoke/CeilTest.h
M libc/test/src/math/smoke/CopySignTest.h
M libc/test/src/math/smoke/FAbsTest.h
M libc/test/src/math/smoke/FDimTest.h
M libc/test/src/math/smoke/FMaxTest.h
M libc/test/src/math/smoke/FMaximumMagNumTest.h
M libc/test/src/math/smoke/FMaximumMagTest.h
M libc/test/src/math/smoke/FMaximumNumTest.h
M libc/test/src/math/smoke/FMaximumTest.h
M libc/test/src/math/smoke/FMinTest.h
M libc/test/src/math/smoke/FMinimumMagNumTest.h
M libc/test/src/math/smoke/FMinimumMagTest.h
M libc/test/src/math/smoke/FMinimumNumTest.h
M libc/test/src/math/smoke/FMinimumTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FloorTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/FrexpTest.h
M libc/test/src/math/smoke/FromfpTest.h
M libc/test/src/math/smoke/FromfpxTest.h
M libc/test/src/math/smoke/HypotTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/LogbTest.h
M libc/test/src/math/smoke/ModfTest.h
M libc/test/src/math/smoke/NextAfterTest.h
M libc/test/src/math/smoke/NextDownTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/NextUpTest.h
M libc/test/src/math/smoke/RIntTest.h
M libc/test/src/math/smoke/RemQuoTest.h
M libc/test/src/math/smoke/RoundEvenTest.h
M libc/test/src/math/smoke/RoundTest.h
M libc/test/src/math/smoke/RoundToIntegerTest.h
M libc/test/src/math/smoke/SqrtTest.h
M libc/test/src/math/smoke/TruncTest.h
M libc/test/src/math/smoke/UfromfpTest.h
M libc/test/src/math/smoke/UfromfpxTest.h
M libc/test/src/math/smoke/nan_test.cpp
M libc/test/src/math/smoke/nanf128_test.cpp
M libc/test/src/math/smoke/nanf_test.cpp
M libc/test/src/math/smoke/nanl_test.cpp
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
[libc] Make fenv and math tests preserve fenv_t state (#89658)
This adds a new test fixture class FEnvSafeTest (usable as a base
class for other fixtures) that ensures each test doesn't perturb
the `fenv_t` state that the next test will start with. It also
provides types and methods tests can use to explicitly wrap code
under test either to check that it doesn't perturb the state or
to save and restore the state around particular test code.
All the fenv and math tests are updated to use this so that none
can affect another. Expectations that code under test and/or
tests themselves don't perturb state can be added later.
Commit: 4e9decf294a19d0047da3aada980f24d19d6c62c
https://github.com/llvm/llvm-project/commit/4e9decf294a19d0047da3aada980f24d19d6c62c
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M libcxx/src/time_zone.cpp
M libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
Log Message:
-----------
[libc++][TZDB] Fixes reverse time lookups. (#89502)
Testing with the get_info() returning a local_info revealed some issues
in the reverse lookup. This needed an additional quirk. Also the
skipping when not in the current continuation optimization was wrong. It
prevented merging two sys_info objects.
Commit: edf733bc321d6e2d0a7dae04ef78d6b291f14a55
https://github.com/llvm/llvm-project/commit/edf733bc321d6e2d0a7dae04ef78d6b291f14a55
Author: Kazu Hirata <kazu at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/MemProf.cpp
Log Message:
-----------
[memprof] Take Schema into account in PortableMemInfoBlock::serializedSize (#89824)
PortableMemInfoBlock::{serialize,deserialize} take Schema into
account, allowing us to serialize/deserialize a subset of the fields.
However, PortableMemInfoBlock::serializedSize does not. That is, it
assumes that all fields are always serialized and deserialized. In
other words, if we choose to serialize/deserialize a subset of the
fields, serializedSize would claim more storage than we actually need.
This patch fixes the problem by teaching serializedSize to take Schema
into account. For now, this patch has no effect on the actual indexed
MemProf profile because we serialize/deserialize all fields, but that
might change in the future.
Aside from check-llvm, I tested this patch by verifying that
llvm-profdata generates bit-wise identical files for each version for
a large raw MemProf file I have.
Commit: 6b8d385ffe047b61a6614d2f8be206429faa28f5
https://github.com/llvm/llvm-project/commit/6b8d385ffe047b61a6614d2f8be206429faa28f5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
AMDGPU: Fix missing intrinsic mangling suffixes in test
Commit: 859de94536425376244940e190e069a09d797737
https://github.com/llvm/llvm-project/commit/859de94536425376244940e190e069a09d797737
Author: Roland McGrath <mcgrathr at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M libc/test/UnitTest/FEnvSafeTest.cpp
Log Message:
-----------
[libc] Fix aarch64 build error in FEnvSafeTest change (#89826)
Commit: 5ac744d72ad2a8d04e0ae869c4e30558dd8058e3
https://github.com/llvm/llvm-project/commit/5ac744d72ad2a8d04e0ae869c4e30558dd8058e3
Author: Andy Kaylor <andrew.kaylor at intel.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/docs/Security.rst
Log Message:
-----------
[Nomination] New Intel representative for the security group (#89435)
Sergey Malsov has left Intel. I would like to nominate Will Huhn to replace him as an Intel representative in the LLVM security group. Will is a security champion for the Intel compiler team. I believe he will be a valuable addition to the LLVM security group as a second representative from Intel. He has more security-specific expertise than me. I regularly consult with Will about topics the LLVM security group is considering, and it will be useful to have him more directly involved.
Commit: ef5906989ae2004100ff56dc5ab59be2be9d5c99
https://github.com/llvm/llvm-project/commit/ef5906989ae2004100ff56dc5ab59be2be9d5c99
Author: Nicolas van Kempen <nvankemp at gmail.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string.h
M clang-tools-extra/test/clang-tidy/checkers/abseil/redundant-strcat-calls.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
Log Message:
-----------
[clang-tidy][modernize-use-starts-ends-with] Add support for compare() (#89530)
Using `compare` is the next most common roundabout way to express
`starts_with` before it was added to the standard. In this case, using
`starts_with` is a readability improvement. Extend existing
`modernize-use-starts-ends-with` to cover this case.
```
// The following will now be replaced by starts_with().
string.compare(0, strlen("prefix"), "prefix") == 0;
string.compare(0, 6, "prefix") == 0;
string.compare(0, prefix.length(), prefix) == 0;
string.compare(0, prefix.size(), prefix) == 0;
```
Commit: 418212089e95e2d39d2997699a149a09d4c5185c
https://github.com/llvm/llvm-project/commit/418212089e95e2d39d2997699a149a09d4c5185c
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M libc/config/linux/syscall_numbers.h.inc
M libc/src/sys/stat/linux/chmod.cpp
Log Message:
-----------
[libc] adding linux SYS_fchmodat2 syscall. (#89819)
Commit: 36209d366d833263d71df328ecca75cf144b1893
https://github.com/llvm/llvm-project/commit/36209d366d833263d71df328ecca75cf144b1893
Author: Andrei Safronov <safronov at espressif.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
A llvm/lib/Target/Xtensa/XtensaCallingConv.td
A llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
A llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.h
M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
A llvm/lib/Target/Xtensa/XtensaOperators.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
A llvm/lib/Target/Xtensa/XtensaUtils.cpp
A llvm/lib/Target/Xtensa/XtensaUtils.h
A llvm/test/CodeGen/Xtensa/call.ll
A llvm/test/CodeGen/Xtensa/calling-conv.ll
A llvm/test/CodeGen/Xtensa/constantpool.ll
A llvm/test/CodeGen/Xtensa/stack-access.ll
M llvm/test/MC/Xtensa/Core/invalid.s
A llvm/test/MC/Xtensa/directive-literal.s
A llvm/test/MC/Xtensa/invalid-literal.s
Log Message:
-----------
[Xtensa] Implement base CallConvention. (#83280)
Implement base Calling Convention functionality.
Implement stack load/store register operations.
Implement call lowering.
Commit: e1321fafbc024007023ce5d9b88d987a920c3bca
https://github.com/llvm/llvm-project/commit/e1321fafbc024007023ce5d9b88d987a920c3bca
Author: Pranav Kant <prka at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTWriter.cpp
R clang/test/SemaCXX/PR41441.cpp
Log Message:
-----------
Revert "Reapply "[Clang][Sema] placement new initializes typedef array with correct size (#83124)" (#89036)"
This reverts commit 74cab546825b32f24e44d69942cdbdd129160471.
Commit: 733a87783cfac7e6bac2c14bc3749ddca879e2be
https://github.com/llvm/llvm-project/commit/733a87783cfac7e6bac2c14bc3749ddca879e2be
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/tools/driver/cc1_main.cpp
M flang/lib/Frontend/FrontendActions.cpp
M lld/ELF/Arch/RISCV.cpp
R llvm/include/llvm/Support/RISCVISAInfo.h
A llvm/include/llvm/Support/RISCVISAUtils.h
A llvm/include/llvm/TargetParser/RISCVISAInfo.h
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Support/CMakeLists.txt
R llvm/lib/Support/RISCVISAInfo.cpp
A llvm/lib/Support/RISCVISAUtils.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/unittests/Support/CMakeLists.txt
R llvm/unittests/Support/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/CMakeLists.txt
A llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
Log Message:
-----------
[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)
This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.
This will allow us to generate part of RISCVISAInfo.cpp using tablegen.
Commit: 0c0c5c475857e9cd6a2fe82fd1e46abdb174a1c1
https://github.com/llvm/llvm-project/commit/0c0c5c475857e9cd6a2fe82fd1e46abdb174a1c1
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
Log Message:
-----------
[gn build] Port 733a87783cfa
Commit: 688c10d23630a23e7bb63804de117d1f281c4961
https://github.com/llvm/llvm-project/commit/688c10d23630a23e7bb63804de117d1f281c4961
Author: Pranav Kant <prka at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
Log Message:
-----------
[Bazel][libc] Fix breakage after 837dab96d6f5bece79fd58d28ea2e6f7c0912493
Commit: 4f4ebee10ec91becb75ed36608ae26a2bd09e3bb
https://github.com/llvm/llvm-project/commit/4f4ebee10ec91becb75ed36608ae26a2bd09e3bb
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan] Eliminate non-deterministic behavior in the pass (#89831)
Almost NFC, instrumentation is as correct as it was before.
We need InstrumentationList grouped by origin instruction,
so we used stable_sort. However these objects already grouped
because we never interleave sequences of `insertShadowCheck`
of different instrunction.
Pointer sort has artifact that it was deppendent on allocator behavior,
so we could inserted checks in a different order.
There is no test, as I failed to reproduce this with `opt`. My guess
is that for reproducer we need to increase fragmentation in the
allocator.
Commit: d56f08b2ba439e88d026a75ff6ec443ac81a3260
https://github.com/llvm/llvm-project/commit/d56f08b2ba439e88d026a75ff6ec443ac81a3260
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
A clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp
A clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/return-const-ref-from-parameter.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp
Log Message:
-----------
[tidy] add new check bugprone-return-const-ref-from-parameter (#89497)
Commit: 3fa6b9c69e27ca77f8c3929dc7908e727765cc4a
https://github.com/llvm/llvm-project/commit/3fa6b9c69e27ca77f8c3929dc7908e727765cc4a
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Sema/SemaRISCVVectorLookup.cpp
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vreinterpret.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_ext_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_trunc_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vreinterpret.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[clang][RISCV] Support RVV bfloat16 C intrinsics (#89354)
It follows the interface defined here:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293
Commit: fd4399cb11f4069888bc7eac01f74493b5a2af48
https://github.com/llvm/llvm-project/commit/fd4399cb11f4069888bc7eac01f74493b5a2af48
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/test/API/macosx/ctf/Makefile
M lldb/test/API/macosx/ctf/TestCTF.py
M lldb/test/API/macosx/ctf/test.c
Log Message:
-----------
[lldb] Fix crash in SymbolFileCTF::ParseFunctions (#89845)
Make SymbolFileCTF::ParseFunctions resilient against not being able to
resolve the argument or return type of a function. ResolveTypeUID can
fail for a variety of reasons so we should always check its result.
The type that caused the crash was `_Bool` which we didn't recognize
as a basic type. This commit also fixes the underlying issue and adds
a test.
rdar://126943722
Commit: 9c4735e9b3be717eaf1ea524842b5968bf2c6513
https://github.com/llvm/llvm-project/commit/9c4735e9b3be717eaf1ea524842b5968bf2c6513
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
Log Message:
-----------
[gn build] Port d56f08b2ba43
Commit: 99e7350235055654aaa923701bf36adaf01739d0
https://github.com/llvm/llvm-project/commit/99e7350235055654aaa923701bf36adaf01739d0
Author: Fangrui Song <i at maskray.me>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
A lld/test/ELF/lto/i386-global-offset-table.ll
A lld/test/ELF/lto/x86-64-global-offset-table.ll
M llvm/lib/Object/ModuleSymbolTable.cpp
M llvm/test/LTO/X86/codemodel-2.ll
M llvm/test/LTO/X86/codemodel-3.ll
M llvm/test/LTO/X86/largedatathreshold-1.ll
M llvm/test/LTO/X86/largedatathreshold-2.ll
M llvm/test/LTO/X86/largedatathreshold-3.ll
Log Message:
-----------
IRSymTab: Record _GLOBAL_OFFSET_TABLE_ for ELF x86
In ELF, relocatable files generated for x86-32 and some code models of
x86-64 (medium, large) may reference the special symbol
`_GLOBAL_OFFSET_TABLE_` that is not used in the IR. In an LTO link, if
there is no regular relocatable file referencing the special symbol, the
linker may not define the symbol and lead to a spurious "undefined
symbol" error.
Fix #61101: record that `_GLOBAL_OFFSET_TABLE_` is used in the IR symbol
table.
Note: The `PreservedSymbols` mechanism
(https://reviews.llvm.org/D112595) that just sets `FB_used` is not
applicable.
The `getRuntimeLibcallSymbols` for extracting lazy runtime library
symbols is for symbols that are "always" potentially used, but linkers
don't have the code model information to make a precise decision.
Pull Request: https://github.com/llvm/llvm-project/pull/89463
Commit: 2cbc2e306cbb0c99aa162357dfdd380e97a07e89
https://github.com/llvm/llvm-project/commit/2cbc2e306cbb0c99aa162357dfdd380e97a07e89
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
Log Message:
-----------
[NFC][MC][AArch64] Do not use else after return in `getRelocType` (#89818)
After #89563, we do not use else after return in code corresponding to
`R_AARCH64_AUTH_ABS64` reloc in `getRelocType`. This patch removes use
of else after return in other places in `getRelocType`.
Commit: dc5939d2b395ce2359f6b6c0a855daaf149600d6
https://github.com/llvm/llvm-project/commit/dc5939d2b395ce2359f6b6c0a855daaf149600d6
Author: Pranav Kant <prka at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
Log Message:
-----------
[Bazel][libc] Add fp_test_helper in deps
Commit: d97cdd7d088b11b45038112a5f7fe5cbf60a6461
https://github.com/llvm/llvm-project/commit/d97cdd7d088b11b45038112a5f7fe5cbf60a6461
Author: Kai Luo <lkail at cn.ibm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
Log Message:
-----------
[PowerPC] Add PPC prefix to retglue ISD node. NFC. (#89771)
So that aligned with other targets.
Commit: a1b1c4a6d1d52916c5d885170a5f54632d579cdc
https://github.com/llvm/llvm-project/commit/a1b1c4a6d1d52916c5d885170a5f54632d579cdc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
Log Message:
-----------
[InstCombine] Fix miscompile in negation of select (#89698)
Swapping the operands of a select is not valid if one hand is more
poisonous that the other, because the negation zero contains poison
elements.
Fix this by adding an extra parameter to isKnownNegation() to forbid
poison elements.
I've implemented this using manual checks to avoid needing four variants
for the NeedsNSW/AllowPoison combinations. Maybe there is a better way
to do this...
Fixes https://github.com/llvm/llvm-project/issues/89669.
Commit: 7339f7ba3053db7595ece1ca5f49bd2e4c3c8305
https://github.com/llvm/llvm-project/commit/7339f7ba3053db7595ece1ca5f49bd2e4c3c8305
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select.ll
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[InstCombine] Fix poison propagation in select of bitwise fold (#89701)
We're replacing the select with the false value here, but it may be more
poisonous if m_Not contains poison elements. Fix this by introducing a
m_NotForbidPoison matcher and using it here.
Fixes https://github.com/llvm/llvm-project/issues/89500.
Commit: cc73c5cca10b65712cb845039e28491c8379a939
https://github.com/llvm/llvm-project/commit/cc73c5cca10b65712cb845039e28491c8379a939
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Remove implication of F extension for XTHeadFMemIdx from RISCVFeatures.td.
There is no implies rule in RISCVISAInfo.cpp so this makes them
consistent.
Soon RISCVFeatures.td will be used to generate RISCVISAInfo.cpp so
it won't be possible to mismatch.
Commit: 469c8a0a4ef9edae4e236d554901e60b2adca074
https://github.com/llvm/llvm-project/commit/469c8a0a4ef9edae4e236d554901e60b2adca074
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Correctly annotate list init braces of class types (#89706)
Fixes #71939.
Commit: d9715c698c4940e65e9bd036e22fb5cab3aa2c6f
https://github.com/llvm/llvm-project/commit/d9715c698c4940e65e9bd036e22fb5cab3aa2c6f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/rv32zacas-invalid.s
M llvm/test/MC/RISCV/rv32zacas-valid.s
M llvm/test/MC/RISCV/rv64zacas-valid.s
M llvm/test/MC/RISCV/rvzabha-invalid.s
M llvm/test/MC/RISCV/rvzabha-valid.s
M llvm/test/MC/RISCV/rvzabha-zacas-valid.s
Log Message:
-----------
[RISCV] Don't make Zacas or Zabha imply A in RISCVISAInfo.cpp
Zabha and Zacas are both documented as depending on Zaamo. I'm
hesitant to make them imply Zaamo instead.
So remove the implication and replace with a check that either
A or Zaamo is enabled.
Commit: aa1e912a1569d46a3b18c73367791a58a9c2b35d
https://github.com/llvm/llvm-project/commit/aa1e912a1569d46a3b18c73367791a58a9c2b35d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/loadstore-alignment.ll
M llvm/test/Transforms/InstCombine/memcpy-from-global.ll
M llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
Log Message:
-----------
[InstCombine] Fix symbol conflicts in tests (NFC)
These tests break when regenerated due to symbol conflicts.
Commit: ba702aa067c0659d2263d2144d38666efa4a1750
https://github.com/llvm/llvm-project/commit/ba702aa067c0659d2263d2144d38666efa4a1750
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/test/Transforms/InstSimplify/ConstProp/gep-alias.ll
M llvm/test/Transforms/InstSimplify/past-the-end.ll
Log Message:
-----------
[InstSimplify] Regenerate test checks (NFC)
Commit: da1e3e8b9ab76e7dc6de1fa41116983cb7d0c510
https://github.com/llvm/llvm-project/commit/da1e3e8b9ab76e7dc6de1fa41116983cb7d0c510
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/test/lit.cfg.py
Log Message:
-----------
[LIT][NVPTX] Add a few more known ptxas versions (#89761)
This patch adds known ptxas versions up to 12.4,
to have tests targeting them.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: c8c1e4e0e576f6e735a55dca4a2eb75ce73ee1db
https://github.com/llvm/llvm-project/commit/c8c1e4e0e576f6e735a55dca4a2eb75ce73ee1db
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/test/Preprocessor/wasm-target-features.c
Log Message:
-----------
[WebAssembly] Fix uses of -DAG and -NOT in wasm-target-features.c (#89777)
We are currently using `PREFIX-DAG` and `PREFIX-NOT` within a single
`PREFIX` test in a mixed way, but `-DAG` and `-NOT` do not work that
way. For example:
Result:
```
1
2
3
```
Test file:
```c
// CHECK-DAG: 3
// CHECK-DAG: 1
// CHECK-NOT: 2
```
This does not work. The last line `CHECK-NOT: 2` does not trigger any
error, because we've already covered all three lines (1~3) while
matching `CHECK-DAG: 3` and `CHECK-DAG: 1`, and FileCheck tries to check
the line `CHECK-NOT: 2` _after_ the line `3`.
Actually, we have
```c
// BLEEDING-EDGE-NOT:#define __wasm_reference_types__ 1{{$}}
```
even though reference-types is enabled in 'bleeding-edge' config, and
this has not triggered any error.
This section
(https://llvm.org/docs/CommandGuide/FileCheck.html#the-check-dag-directive)
explains the interactions between `CHECK-DAG` and `CHECK-NOT`s:
> As a result, the surrounding `CHECK-DAG:` directives cannot be
reordered, i.e. all occurrences matching `CHECK-DAG:` before
`CHECK-NOT:` must not fall behind occurrences matching `CHECK-DAG:`
after `CHECK-NOT:`.
So in order to test the 'include' lists and 'not-include' lists, we have
to run the tests twice with different prefixes. This splits `GENERIC`
and `BLEEDING-EDGE` tests in two configs (`***-INCLUDE` and `***`) to
test them correctly.
This also adds some spaces after colons, sorts the feature lists, and
adds `1{{$}}` to the `MVP` tests to make them consistent with `GENERIC`
and `BLEEDING-EDGE` tests.
Commit: 88b6186af3908c55b357858eb348b5143f21c289
https://github.com/llvm/llvm-project/commit/88b6186af3908c55b357858eb348b5143f21c289
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/test/Preprocessor/wasm-target-features.c
Log Message:
-----------
[WebAssembly] Tidy up wasm-target-features.c (#89778)
This tidies up `wasm-target-features.c` cosmetically:
- Sorts the feature tests alphabetically
- Adds a space after colons
Commit: b82a4bfb54284d96ab065596620e260319045330
https://github.com/llvm/llvm-project/commit/b82a4bfb54284d96ab065596620e260319045330
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Remove unnecessary cast of nullptr in std::fill call. NFC
Commit: 6493da7356541becdf2bf6c141fd619c15dec5d6
https://github.com/llvm/llvm-project/commit/6493da7356541becdf2bf6c141fd619c15dec5d6
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/pr89833.ll
Log Message:
-----------
[RISCV] Use the store value's VT as the MemoryVT after combining riscv.masked.strided.store (#89874)
According to `RISCVTargetLowering::getTgtMemIntrinsic`, the MemoryVT
is the scalar element VT for strided store and the MemoryVT is the
same as the store value's VT for unit-stride store.
After combining `riscv.masked.strided.store` to `masked.store`, we
just use the scalar element VT to construct `masked.store`, which is
wrong.
With wrong MemoryVT, the DAGCombiner will combine `trunc+masked.store`
to truncated `masked.store` because `TLI.canCombineTruncStore` returns
true.
So, we should use the store value's VT as the MemoryVT.
This fixes #89833.
Commit: 805d5637a0d50caa073f435b55940c1338aae0fc
https://github.com/llvm/llvm-project/commit/805d5637a0d50caa073f435b55940c1338aae0fc
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaCXX/template-specialization.cpp
Log Message:
-----------
[clang] Mark ill-formed partial specialization as invalid (#89536)
Fixes #89374
Solution suggested by @cor3ntin
Commit: cf328ff96daf5e676fb51ac86e550af7fd689fec
https://github.com/llvm/llvm-project/commit/cf328ff96daf5e676fb51ac86e550af7fd689fec
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/docs/MemoryModelRelaxationAnnotations.rst
M llvm/docs/Reference.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
A llvm/include/llvm/IR/MemoryModelRelaxationAnnotations.h
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/IR/CMakeLists.txt
M llvm/lib/IR/Instruction.cpp
A llvm/lib/IR/MemoryModelRelaxationAnnotations.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
A llvm/test/CodeGen/AMDGPU/mmra.ll
A llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll
A llvm/test/Transforms/SimplifyCFG/mmra.ll
A llvm/test/Verifier/mmra-allowed.ll
A llvm/test/Verifier/mmra.ll
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp
Log Message:
-----------
[IR] Memory Model Relaxation Annotations (#78569)
Implements the core/target-agnostic components of Memory Model
Relaxation Annotations.
RFC:
https://discourse.llvm.org/t/rfc-mmras-memory-model-relaxation-annotations/76361/5
Commit: 806db47b060b6e70cc71ee5ce8052829f85e6469
https://github.com/llvm/llvm-project/commit/806db47b060b6e70cc71ee5ce8052829f85e6469
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[IR] Remove unused variable in Verifier.cpp (NFC)
llvm-project/llvm/lib/IR/Verifier.cpp:4854:14:
error: unused variable 'IsLeaf' [-Werror,-Wunused-variable]
const auto IsLeaf = [](const Metadata *CurMD) {
^
1 error generated.
Commit: ad4a42bbc7f8d27d8e91b69dbd3282cf873d418e
https://github.com/llvm/llvm-project/commit/ad4a42bbc7f8d27d8e91b69dbd3282cf873d418e
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Log Message:
-----------
[RISCV] Remove -riscv-split-regalloc flag (#89715)
Split vector and scalar regalloc has been enabled by default for 5
months now since d0a39e617ba301a76d28e2d82e1f657999c9dcfb, and shipped
with 18.1.0. I haven't heard of any issues with it so far, so this
proposes to remove the flag to reduce the number of configurations we
have to support.
Commit: 7da63426ac5d9719038842c30ca2a644620be071
https://github.com/llvm/llvm-project/commit/7da63426ac5d9719038842c30ca2a644620be071
Author: Lang Hames <lhames at gmail.com>
Date: 2024-04-23 (Tue, 23 Apr 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.cpp
M llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
M llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp
Log Message:
-----------
Re-apply "[ORC] Unify task dispatch across ExecutionSession..." with more fixes.
This re-applies 6094b3b7db7, which was reverted in e7efd37c229 (and before that
in 1effa19de24) due to bot failures.
The test failures were fixed by having SelfExecutorProcessControl use an
InPlaceTaskDispatcher by default, rather than a DynamicThreadPoolTaskDispatcher.
This shouldn't be necessary (and indicates a concurrency issue elsewhere), but
InPlaceTaskDispatcher is a less surprising default, and better matches the
existing behavior (compilation on current thread by default), so the change
seems reasonable. I've filed https://github.com/llvm/llvm-project/issues/89870
to investigate the concurrency issue as a follow-up.
Coding my way home: 6.25133S 127.94177W
Commit: 9375962ac9e8d8e83fa8e32c3b04bb6970e4b242
https://github.com/llvm/llvm-project/commit/9375962ac9e8d8e83fa8e32c3b04bb6970e4b242
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/test/TableGen/ContextlessPredicates.td
M llvm/test/TableGen/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
M llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
M llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-input-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
M llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
M llvm/test/TableGen/GlobalISelEmitterFlags.td
M llvm/test/TableGen/GlobalISelEmitterHwModes.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
M llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
M llvm/test/TableGen/GlobalISelEmitterRegSequence.td
M llvm/test/TableGen/GlobalISelEmitterSubreg.td
M llvm/test/TableGen/GlobalISelEmitterVariadic.td
M llvm/test/TableGen/HasNoUse.td
M llvm/test/TableGen/address-space-patfrags.td
M llvm/test/TableGen/gisel-physreg-input.td
M llvm/test/TableGen/immarg-predicated.td
M llvm/test/TableGen/immarg.td
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
Log Message:
-----------
[TableGen][GlobalISel] Specialize more MatchTable Opcodes (#89736)
The vast majority of the following (very common) opcodes were always
called with identical arguments:
- `GIM_CheckType` for the root
- `GIM_CheckRegBankForClass` for the root
- `GIR_Copy` between the old and new root
- `GIR_ConstrainSelectedInstOperands` on the new root
- `GIR_BuildMI` to create the new root
I added overloaded version of each opcode specialized for the root
instructions. It always saves between 1 and 2 bytes per instance
depending on the number of arguments specialized into the opcode. Some
of these opcodes had between 5 and 15k occurences in the AArch64
GlobalISel Match Table.
Additionally, the following opcodes are almost always used in the same
sequence:
- `GIR_EraseFromParent 0` + `GIR_Done`
- `GIR_EraseRootFromParent_Done` has been created to do both. Saves 2
bytes per occurence.
- `GIR_IsSafeToFold` was *always* called for each InsnID except 0.
- Changed the opcode to take the number of instructions to check after
`MI[0]`
The savings from these are pretty neat. For `AArch64GenGlobalISel.inc`:
- `AArch64InstructionSelector.cpp.o` goes down from 772kb to 704kb (-10%
code size)
- Self-reported MatchTable size goes from 420380 bytes to 352426 bytes
(~ -17%)
A smaller match table means a faster match table because we spend less
time iterating and decoding.
I don't have a solid measurement methodology for GlobalISel performance
so I don't have precise numbers but I saw a few % of improvements in a
simple testcase.
Commit: 008b7f1dfdba5cd0479cbb0348d84d0eeb8b5d46
https://github.com/llvm/llvm-project/commit/008b7f1dfdba5cd0479cbb0348d84d0eeb8b5d46
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/HostAssociations.cpp
M flang/test/Lower/HLFIR/internal-procedures.f90
Log Message:
-----------
[flang] implement capture of procedure pointers in internal procedures (#89619)
Commit: 46b011d0ccb468613bcc7e9e756518f9f383001d
https://github.com/llvm/llvm-project/commit/46b011d0ccb468613bcc7e9e756518f9f383001d
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn build] Port cf328ff96daf
Commit: 9a8235a290b87a311217b9ffd811de06bff38746
https://github.com/llvm/llvm-project/commit/9a8235a290b87a311217b9ffd811de06bff38746
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Fix -Wunused-variable in LLJIT.cpp (NFC)
llvm-project/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp:684:8:
error: unused variable 'ConcurrentCompilationSettingDefaulted' [-Werror,-Wunused-variable]
bool ConcurrentCompilationSettingDefaulted = !SupportConcurrentCompilation;
^
1 error generated.
Commit: 78ebaa2d798f939e35e44778572eb54c4bf36550
https://github.com/llvm/llvm-project/commit/78ebaa2d798f939e35e44778572eb54c4bf36550
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Fix build failure (NFC)
Commit: b3ca9c30dedf28ecf687779294c1343a840bfd35
https://github.com/llvm/llvm-project/commit/b3ca9c30dedf28ecf687779294c1343a840bfd35
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/test/Analysis/ValueTracking/known-non-zero.ll
Log Message:
-----------
[ValueTracking] Add tests for isKnowNonZero of `trunc nuw/nsw`; NFC
Commit: b933c8447b2a8797a882d3506460f49fb6f7bf34
https://github.com/llvm/llvm-project/commit/b933c8447b2a8797a882d3506460f49fb6f7bf34
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Analysis/ValueTracking/known-non-zero.ll
Log Message:
-----------
[ValueTracking] Add support for `trunc nuw/nsw` in isKnowNonZero
With `nsw`/`nuw`, the `trunc` is non-zero if its operand is non-zero.
Proofs: https://alive2.llvm.org/ce/z/iujmk6
Closes #89643
Commit: 62db43497fb019d0ac0677ae0c9ea2eba136b230
https://github.com/llvm/llvm-project/commit/62db43497fb019d0ac0677ae0c9ea2eba136b230
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M lldb/docs/conf.py
Log Message:
-----------
[lldb] Enable support for Markdown documentation pages (#89716)
RST is powerful but usually too powerful for 90% of what we need it for.
Markdown is easier to edit and can be previewed easily without building
the entire website.
This copies what llvm does already, making myst_parser optional if you
only want man pages.
Previously we had Markdown enabled in
8b95bd3310c126e76e0714bea6003a9b1aa739fb but that got reverted. That did
this in a different way but I've gone with the standard llvm set this
time.
I intend the first Markdown pages to be the remote protocol extension
docs, as they are not in any set format right now.
Commit: 662ef8604268b207910225ecca90daf30a46720b
https://github.com/llvm/llvm-project/commit/662ef8604268b207910225ecca90daf30a46720b
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/lib/Serialization/ASTWriter.cpp
Log Message:
-----------
[clang][NFC] Remove useless code in ASTWriter
A follow-up to #71709, addressing the static analysis finding reported in https://github.com/llvm/llvm-project/pull/71709/files#r1576846306
Commit: 71c5964f5c0686be3319bc55a0dbfb0e3a60a917
https://github.com/llvm/llvm-project/commit/71c5964f5c0686be3319bc55a0dbfb0e3a60a917
Author: Tomas Matheson <Tomas.Matheson at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/TargetParser/CMakeLists.txt
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/utils/TableGen/ARMTargetDefEmitter.cpp
M llvm/utils/TableGen/CMakeLists.txt
Log Message:
-----------
[ARM][AArch64] autogenerate header file for TargetParser from Target tablegen files (#88378)
Introduce a mechanism to share data between the ARM and AArch64 backends and
TargetParser, to reduce duplication of code. This is similar to the current
RISC-V implementation.
The target tablegen file (in this case `ARM.td` or `AArch64.td`) is
processed during building of `TargetParser` to generate the following
files in the build tree:
- `build/include/llvm/TargetParser/ARMTargetParserDef.inc`
- `build/include/llvm/TargetParser/AArch64TargetParserDef.inc`
For now, the use of these generated files is limited to files _outside_
of `TargetParser`. The main reason for this is that the modifications to
`TargetParser` will require additional data added to the tablegen files,
which I want to split into separate PRs.
Commit: 69703b1f94ac8e5c03bd39d0a581bf6e553545e4
https://github.com/llvm/llvm-project/commit/69703b1f94ac8e5c03bd39d0a581bf6e553545e4
Author: Lang Hames <lhames at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC] Fix bot failure due to 7da63426ac5 (ORC task dispatch unification).
Fixes the failure at https://lab.llvm.org/buildbot/#/builders/131/builds/62928,
and add comments about unused variable and update debugging output.
Coding my way home: 6.44615S, 128.16704W
Commit: 601d0caf3b347a666b59928e4c3ad6b8e3d1d35c
https://github.com/llvm/llvm-project/commit/601d0caf3b347a666b59928e4c3ad6b8e3d1d35c
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M lldb/docs/index.rst
R lldb/docs/lldb-gdb-remote.txt
A lldb/docs/resources/lldbgdbremote.md
Log Message:
-----------
[lldb][Docs] Convert GDB protocol extensions doc to Markdown and add to website (#89718)
This document has never been on the website, unlike GDB's protocol docs.
It will be useful to have both available online to compare.
Markdown is easier to edit and preview in many editors (including Github
itself), so I've chosen that over RST. Plus, building the website takes
minutes and I lose the will to make nice edits when I have to deal with
that.
The standard dialiect lacks some things notably multi-line table cells,
so I've converted large tables into bullet point lists
so that we still get text wrapping. This is a downside but I think the
simplicity of Markdown outweighs this.
I have applied the plain text markers where I've noticed it and escaped
some HTML characters. There may be more changes needed but, it's
Markdown, so it's in theory a lot easier for someone to fix it!
Commit: c071c1d3abfedaf081d77308a24bb38c061ff999
https://github.com/llvm/llvm-project/commit/c071c1d3abfedaf081d77308a24bb38c061ff999
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
A llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
A llvm/test/CodeGen/SPIRV/types/or-i1.ll
Log Message:
-----------
[SPIR-V] New validation tests for pointer and primitive types (#89632)
This patch adds new tests mostly checking SPIR-V validation of pointer
and primitive types.
Commit: 603ba4c59635ff5f8a54d1106719124aee20271d
https://github.com/llvm/llvm-project/commit/603ba4c59635ff5f8a54d1106719124aee20271d
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
Log Message:
-----------
[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)
This patch splits off part of the work to move vsetvli insertion to post
regalloc in #70549.
The doLocalPostpass operates outside of RISCVInsertVSETVLI's dataflow,
so we can move it to its own pass. We can then move it to post vector
regalloc which should be a smaller change.
A couple of things that are different from #70549:
- This manually fixes up the LiveIntervals rather than recomputing it
via createAndComputeVirtRegInterval. I'm not sure if there's much of a
difference with either.
- For the postpass it's sufficient enough to just check isUndef() in
hasUndefinedMergeOp, i.e. we don't need to lookup the def in VNInfo.
Running on llvm-test-suite and SPEC CPU 2017 there aren't any changes in
the number of vsetvlis removed. There are some minor scheduling diffs as
well as extra spills and less spills in some cases (caused by transient
vsetvlis existing between RISCVInsertVSETVLI and RISCVCoalesceVSETVLI
when vec regalloc happens), but they are minor and should go away once
we finish moving the rest of RISCVInsertVSETVLI.
We could also potentially turn off this pass for unoptimised builds.
Commit: 788d1598212b402057889f5eb973b8665a735d04
https://github.com/llvm/llvm-project/commit/788d1598212b402057889f5eb973b8665a735d04
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
A utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
M utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
Log Message:
-----------
[libc][bazel] Allow configure options to alter all targets (#89251)
The previous state was leading to inconsistencies. Some targets would
get the options and some wouldn't. As an example, the `MEMORY_COPTS`
definitions would only apply to the `:string_memory_utils` target but
not to the `:memcpy` target. This patch makes sure definitions are
applied throughout the LLVM libc targets as `local_defines`. This
ensures that the preprocessor definitions don't propagate to depending
targets outside of LLVM libc, and that all libc targets have consistent
preprocessor definitions.
Commit: 46163688e111956a9aeb3a35b8f85a40ef7035d0
https://github.com/llvm/llvm-project/commit/46163688e111956a9aeb3a35b8f85a40ef7035d0
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
Log Message:
-----------
[AMDGPU] Allow WorkgroupID intrinsics in amdgpu_gfx functions (#89773)
With GFX12 architected SGPRs the workgroup ids are trivially available
in any function called from a compute entrypoint.
Commit: 91526d64a8adb14edc55adfd5270858791822837
https://github.com/llvm/llvm-project/commit/91526d64a8adb14edc55adfd5270858791822837
Author: Martin Storsjö <martin at martin.st>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M libcxx/modules/std.compat/cstdlib.inc
Log Message:
-----------
[libcxx] [modules] Add _LIBCPP_USING_IF_EXISTS on aligned_alloc (#89827)
This is missing e.g. on Windows. With this change, it's possible to make
the libcxx std module work on mingw-w64 (although that requires a few
fixes to those headers).
In the regular cstdlib header, we have _LIBCPP_USING_IF_EXISTS flagged
on every single reexported function (since
a9c9183ca42629fa83cdda297d1d30c7bc1d7c91), but the modules seem to only
have _LIBCPP_USING_IF_EXISTS set on a few individual functions, so far.
Commit: d149370900844cca3fec06bb078eb8d85008f72d
https://github.com/llvm/llvm-project/commit/d149370900844cca3fec06bb078eb8d85008f72d
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/rvv/commutable.ll
Log Message:
-----------
[RISCV] Add test coverage for commutable RVV instructions
This patch adds test coverage for commutable RVV instructions
added in #88379.
For each kind of instruction, I add two tests (one for unmasked and
one for masked). These tests don't cover all the SEWs/LMULs as I
think it's not worthy because there is no difference when handling
instructions with different SEWs/LMULs.
As the tests shown, we can't eliminate two equal instructions if
there is a use of `V0`. This may be fixed in the future.
Reviewers: asb, jacquesguan, topperc, lukel97, preames
Reviewed By: lukel97
Pull Request: https://github.com/llvm/llvm-project/pull/89889
Commit: 945eeb2d92758ef907ef3aeb3251fadc64b731b3
https://github.com/llvm/llvm-project/commit/945eeb2d92758ef907ef3aeb3251fadc64b731b3
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/add4.ll
Log Message:
-----------
[InstCombine] Simplify `(X / C0) * C1 + (X % C0) * C2` to `(X / C0) * (C1 - C2 * C0) + X * C2` (#76285)
Since `DivRemPairPass` runs after `ReassociatePass` in the optimization
pipeline, I decided to do this simplification in `InstCombine`.
Alive2: https://alive2.llvm.org/ce/z/Jgsiqf
Fixes #76128.
Commit: e400e908b2d97529b1a65dd0bdad80d481c39527
https://github.com/llvm/llvm-project/commit/e400e908b2d97529b1a65dd0bdad80d481c39527
Author: Lang Hames <lhames at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
Log Message:
-----------
[ORC] Fix SpeculativeJIT example after 7da63426ac5 (ORC dispatch unification).
Fixes the bot failure at
https://lab.llvm.org/buildbot/#/builders/272/builds/14788.
Coding my way home: 6.48551S, 128.21109W
Commit: effb2f1917f11b58262d0e13aa085303b5896852
https://github.com/llvm/llvm-project/commit/effb2f1917f11b58262d0e13aa085303b5896852
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
[libclc] Use a response file when building on Windows (#89756)
We've recently seen the libclc llvm-link invocations become so long that
they exceed the character limits on certain platforms.
Using a 'response file' should solve this by offloading the list of
inputs into a separate file, and using special syntax to pass it to
llvm-link. Note that neither the response file nor syntax aren't
specific to Windows but we restrict it to that platform regardless. We
have the option of expanding it to other platforms in the future.
Commit: 4c3b0a6e009228e8c45586eea7a1f7955d36dd42
https://github.com/llvm/llvm-project/commit/4c3b0a6e009228e8c45586eea7a1f7955d36dd42
Author: Jack Frankland <jack.frankland at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
Log Message:
-----------
[mlir][tosa] Fix Map for Bias Broadcast (#89059)
Commit: 282b56f43d5dfac1dda548924e91fbc380451603
https://github.com/llvm/llvm-project/commit/282b56f43d5dfac1dda548924e91fbc380451603
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
Log Message:
-----------
[VectorCombine] foldShuffleOfBinops - add support for length changing shuffles (#88899)
Refactor to be closer to foldShuffleOfCastops - sibling patch to #88743 that can be used to address some of the issues identified in #88693
Commit: 89d125564a619068cead98c970215e69653503e8
https://github.com/llvm/llvm-project/commit/89d125564a619068cead98c970215e69653503e8
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll
Log Message:
-----------
Bit width of input/result types in OpSConvert/OpUConvert must not be the same (#89737)
This PR fixes the issue
https://github.com/llvm/llvm-project/issues/88908
Attached test case is updated to check that OpSConvert/OpUConvert is not
generated when input and result types are identical.
Commit: 486ea1ec6e436d502064b610027361523adc537b
https://github.com/llvm/llvm-project/commit/486ea1ec6e436d502064b610027361523adc537b
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
A llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll
Log Message:
-----------
[SPIR-V] Fix pre-legalizer pass in SPIR-V Backend to support more gMIR opcode inserted by IRTranslator (#89890)
Translating global values, IRTranslator pass can sometimes generates
code patterns that require additional efforts during pre-legalization.
This PR addresses this problem to support G_PTRTOINT instruction used in
initialization of GV.
Commit: 18bf0c3c1d07fb5ccde9ce91473568668d5df8e2
https://github.com/llvm/llvm-project/commit/18bf0c3c1d07fb5ccde9ce91473568668d5df8e2
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
A flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
Log Message:
-----------
[flang][OpenMP] fix reduction of arrays with non-default lower bounds (#89611)
It turned out that `hlfir::genVariableBox` didn't add lower bounds to
the boxes it created. Using a shapeshift instead of only a shape adds
the lower bounds information to the thread-local copy of the box.
Fixes #89259
Commit: ceca523581c60a7034429645b7f7401d4eec8379
https://github.com/llvm/llvm-project/commit/ceca523581c60a7034429645b7f7401d4eec8379
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/test/Driver/bbc-mlir-pass-pipeline.f90
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/array-value-copy-2.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Fir/loop01.fir
M flang/test/Fir/loop02.fir
M flang/test/Lower/OpenMP/FIR/flush.f90
M flang/test/Lower/OpenMP/FIR/master.f90
M flang/test/Lower/OpenMP/FIR/parallel-sections.f90
M flang/test/Transforms/omp-reduction-cfg-conversion.fir
Log Message:
-----------
[flang] de-duplicate CFGConversion pass (#89783)
See RFC at
https://discourse.llvm.org/t/rfc-add-an-interface-for-top-level-container-operations
I previously did the same for the AbstractResult pass
https://github.com/llvm/llvm-project/pull/88867
Commit: b8e97f0768f2b537c45930f56f4027a4c0a07f24
https://github.com/llvm/llvm-project/commit/b8e97f0768f2b537c45930f56f4027a4c0a07f24
Author: Tomas Matheson <tomas.matheson at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/utils/TableGen/CMakeLists.txt
Log Message:
-----------
[ARM] Add ARMTargetDefEmitter to llvm-tblgen source
Missed from #88378, only showed up in the sanitizer builds.
Commit: 3cb660d772ecc4605196ba65f09c4117e8435ef3
https://github.com/llvm/llvm-project/commit/3cb660d772ecc4605196ba65f09c4117e8435ef3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
Log Message:
-----------
DAG: Fix missing fptrunc_round name in debug dumps
Commit: e5de95d6dc1346dade17cb2c8ffe6005e873f4a2
https://github.com/llvm/llvm-project/commit/e5de95d6dc1346dade17cb2c8ffe6005e873f4a2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
Log Message:
-----------
[RISCV] bitreverse-shift.ll - fix typo
Noticed in #89897
Commit: 506c84a7198630b7476b02d985c6ed09338f757d
https://github.com/llvm/llvm-project/commit/506c84a7198630b7476b02d985c6ed09338f757d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.h
Log Message:
-----------
[TTI] getArithmeticInstrCost - use std:nullopt to create default empty `ArrayRef<const Value *> Args` argument. NFC.
Commit: 4d3308202e52b213a05023c8b8b470b346151de6
https://github.com/llvm/llvm-project/commit/4d3308202e52b213a05023c8b8b470b346151de6
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A mlir/test/Examples/NVGPU/Ch0.py
A mlir/test/Examples/NVGPU/Ch1.py
A mlir/test/Examples/NVGPU/Ch2.py
A mlir/test/Examples/NVGPU/Ch3.py
A mlir/test/Examples/NVGPU/Ch4.py
A mlir/test/Examples/NVGPU/Ch5.py
A mlir/test/Examples/NVGPU/lit.local.cfg
A mlir/test/Examples/NVGPU/tools/lit.local.cfg
A mlir/test/Examples/NVGPU/tools/nvdsl.py
A mlir/test/Examples/NVGPU/tools/nvgpucompiler.py
Log Message:
-----------
[mlir][nvgpu] NVGPU Tutorials (#87065)
I have a tutorial at EuroLLVM 2024 ([Zero to Hero: Programming Nvidia
Hopper Tensor Core with MLIR's NVGPU
Dialect](https://llvm.swoogo.com/2024eurollvm/session/2086997/zero-to-hero-programming-nvidia-hopper-tensor-core-with-mlir's-nvgpu-dialect)).
For that, I implemented tutorial codes in Python. The focus is the nvgpu
dialect and how to use its advanced features. I thought it might be
useful to upstream this.
The tutorial codes are as follows:
- **Ch0.py:** Hello World
- **Ch1.py:** 2D Saxpy
- **Ch2.py:** 2D Saxpy using TMA
- **Ch3.py:** GEMM 128x128x64 using Tensor Core and TMA
- **Ch4.py:** Multistage performant GEMM using Tensor Core and TMA
- **Ch5.py:** Warp Specialized GEMM using Tensor Core and TMA
I might implement one more chapter:
- **Ch6.py:** Warp Specialized Persistent ping-pong GEMM
This PR also introduces the nvdsl class, making IR building in the
tutorial easier.
Commit: 333aad7195b568e03db52a561052eba9f73758d5
https://github.com/llvm/llvm-project/commit/333aad7195b568e03db52a561052eba9f73758d5
Author: David Green <david.green at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/concatbinop.ll
Log Message:
-----------
[AArch64] Add tests for concat binop patterns. NFC
Commit: a13ff06dce501d8863b3c7068db87ff790ba8734
https://github.com/llvm/llvm-project/commit/a13ff06dce501d8863b3c7068db87ff790ba8734
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
AMDGPU: Remove dead arguments in test and add SGPR variants
Also cleanup to avoid the memory noise by using return values
in the trivial cases.
Commit: 401658cb4bad619254316ff936c527fec0861472
https://github.com/llvm/llvm-project/commit/401658cb4bad619254316ff936c527fec0861472
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
AMDGPU: Fix vector handling of fptrunc_round
Commit: 01f8da908ca3616c266fd0afb8490b7f7633ef4b
https://github.com/llvm/llvm-project/commit/01f8da908ca3616c266fd0afb8490b7f7633ef4b
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
Log Message:
-----------
[LoopUnroll] Add tests for performing load CSE after unrolling.
Precommit tests for https://github.com/llvm/llvm-project/pull/83860.
Commit: c81ec1f35c8226a13df4e2988d3be7b45ebd4e85
https://github.com/llvm/llvm-project/commit/c81ec1f35c8226a13df4e2988d3be7b45ebd4e85
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[llvm][Bazel] Fix Bazel build for 71c5964f5c0686be3319bc55a0dbfb0e3a60a917
Commit: af81d8ec224900de7a4d2c96a675269499b55a0c
https://github.com/llvm/llvm-project/commit/af81d8ec224900de7a4d2c96a675269499b55a0c
Author: Allen <zhongyunde at huawei.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
Log Message:
-----------
[AArch64][CodeGen] Add patterns for small negative VScale const (#89607)
On AArch64, rdvl can accept a nagative value, while cntd/cntw/cnth can't.
As we do support VScale with a negative multiply value, so we did not limit
the negative value and instead took the hit of having the extra patterns according PR88108.
Also add NoUseScalarIncVL to avoid affecting patterns works for -mattr=+use-scalar-inc-vl
Fix https://github.com/llvm/llvm-project/issues/84620
Commit: 62549dbbf286823e400e07cff5ae219e48c175d2
https://github.com/llvm/llvm-project/commit/62549dbbf286823e400e07cff5ae219e48c175d2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/test/Driver/amdgpu-toolchain.c
Log Message:
-----------
[AMDGPU] Correctly determine the toolchain linker (#89803)
Summary:
The AMDGPU toolchain simply took the short name to get the link job
instead of using the common utilities that respect options like
`-fuse-ld`. Any linker that isn't `ld.lld` will fail, however we should
be able to override it.
Commit: eaa2eac8ec73a0473655f2da73f347906d14b00f
https://github.com/llvm/llvm-project/commit/eaa2eac8ec73a0473655f2da73f347906d14b00f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/test/Driver/amdgpu-toolchain.c
Log Message:
-----------
[AMDGPU] Fix linker test on platforms without BFD
Commit: 9f2a068bffad4a36db088673210f680bfd08b3d1
https://github.com/llvm/llvm-project/commit/9f2a068bffad4a36db088673210f680bfd08b3d1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[DAG] Add getValid*ShiftAmountConstant wrappers without DemandedElts
Simplify callers which don't have their own DemandedElts mask.
Noticed while reviewing #88801
Commit: 6e9ea6ea6897561a9c3bd77b0b93e415fdc7eeb3
https://github.com/llvm/llvm-project/commit/6e9ea6ea6897561a9c3bd77b0b93e415fdc7eeb3
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
Log Message:
-----------
[MLIR][LLVM][Mem2Reg] Extends support for partial stores (#89740)
This commit enhances the LLVM dialect's Mem2Reg interfaces to support
partial stores to memory slots. To achieve this support, the `getStored`
interface method has to be extended with a parameter of the reaching
definition, which is now necessary to produce the resulting value after
this store.
Commit: 79d4d165638b7587937fc60431e0865fd73c9334
https://github.com/llvm/llvm-project/commit/79d4d165638b7587937fc60431e0865fd73c9334
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/lib/Bindings/Python/DialectLLVM.cpp
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/python/mlir/dialects/LLVMOps.td
M mlir/python/mlir/dialects/llvm.py
M mlir/test/python/dialects/llvm.py
Log Message:
-----------
[mlir][python] extend LLVM bindings (#89797)
Add bindings for LLVM pointer type.
Commit: d3f6c2c5a76ed4eafd1ef76bd64cb01c8934c914
https://github.com/llvm/llvm-project/commit/d3f6c2c5a76ed4eafd1ef76bd64cb01c8934c914
Author: Nico Weber <thakis at chromium.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
Log Message:
-----------
[gn] port b8e97f0768f2
Commit: 2bcbe40f8a1c6cc9a256711261d8aa8fde50f7b3
https://github.com/llvm/llvm-project/commit/2bcbe40f8a1c6cc9a256711261d8aa8fde50f7b3
Author: Daniel Grumberg <dgrumberg at apple.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/include/clang/ExtractAPI/API.h
M clang/include/clang/ExtractAPI/APIRecords.inc
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/include/clang/ExtractAPI/ExtractAPIVisitor.h
M clang/lib/ExtractAPI/API.cpp
M clang/lib/ExtractAPI/DeclarationFragments.cpp
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/test/ExtractAPI/anonymous_record_no_typedef.c
M clang/test/ExtractAPI/enum.c
M clang/test/ExtractAPI/function_noexcepts.cpp
M clang/test/ExtractAPI/methods.cpp
M clang/test/ExtractAPI/objc_block.m
M clang/test/ExtractAPI/typedef_anonymous_record.c
M clang/test/ExtractAPI/typedef_struct_enum.c
Log Message:
-----------
[clang][ExtractAPI] Fix handling of anonymous TagDecls (#87772)
This changes the handling of anonymous TagDecls to the following rules:
- If the TagDecl is embedded in the declaration for some VarDecl (this
is the only possibility for RecordDecls), then pretend the child decls
belong to the VarDecl
- If it's an EnumDecl proceed as we did previously, i.e., embed it in
the enclosing DeclContext.
Additionally this fixes a few issues with declaration fragments not
consistently including "{ ... }" for anonymous TagDecls. To make testing
these additions easier this patch fixes some text declaration fragments
merging issues and updates tests accordingly.
rdar://121436298
Commit: 93eeca331e1304e0a75e606ec5a32e8704432c67
https://github.com/llvm/llvm-project/commit/93eeca331e1304e0a75e606ec5a32e8704432c67
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
LangRef: fix broken link
Commit: b87b6e2c880de5ecc4c7b3a8b9b2db09e6149851
https://github.com/llvm/llvm-project/commit/b87b6e2c880de5ecc4c7b3a8b9b2db09e6149851
Author: Nico Weber <thakis at chromium.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
Log Message:
-----------
[gn] port 71c5964f5c0 (-gen-arm-target-def)
Reverts d3f6c2c5a76e, since ARMTargetDefEmitter.cpp has to be in
llvm-min-tblgen too.
Commit: d577518d98c7b93cc7e55ae9aafd0fc1ce38ec0e
https://github.com/llvm/llvm-project/commit/d577518d98c7b93cc7e55ae9aafd0fc1ce38ec0e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMP.h
M llvm/lib/Frontend/OpenMP/OMP.cpp
M llvm/unittests/Frontend/OpenMPCompositionTest.cpp
Log Message:
-----------
[Frontend][OpenMP] Implement getLeafOrCompositeConstructs (#89104)
This function will break up a construct into constituent leaf and
composite constructs, e.g. if OMPD_c_d_e and OMPD_d_e are composite
constructs, then OMPD_a_b_c_d_e will be broken up into the list {OMPD_a,
OMPD_b, OMPD_c_d_e}.
Commit: 9cbf96ad5b6fe777bf5acd43b65abfb062381f8c
https://github.com/llvm/llvm-project/commit/9cbf96ad5b6fe777bf5acd43b65abfb062381f8c
Author: Fabio D'Urso <fdurso at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp
Log Message:
-----------
Allow ZX_ERR_NO_RESOURCES with MAP_ALLOWNOMEM on Fuchsia (#89767)
This can occur if the virtual address space is (almost) entirely
mapped or heavily fragmented.
Commit: bd34bc6dc2e4e60813ddea31bfb4ca46d3a96013
https://github.com/llvm/llvm-project/commit/bd34bc6dc2e4e60813ddea31bfb4ca46d3a96013
Author: Dinar Temirbulatov <Dinar.Temirbulatov at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
M clang/test/Sema/aarch64-sme-func-attrs.c
Log Message:
-----------
[Clang][AArch64] Extend diagnostics when warning non/streaming about vector size difference (#88380)
Add separate messages about passing arguments or returning parameters
with scalable types.
---------
Co-authored-by: Sander de Smalen <sander.desmalen at arm.com>
Commit: 07e6c1609d0a57f7ddc0537b7794be2e0296658b
https://github.com/llvm/llvm-project/commit/07e6c1609d0a57f7ddc0537b7794be2e0296658b
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/CAPI/execution_engine.c
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
M mlir/test/Dialect/LLVMIR/legalize-for-export.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[MLIR][OpenMP] Make omp.wsloop into a loop wrapper (1/5) (#89209)
This patch updates the definition of `omp.wsloop` to enforce the
restrictions of a loop wrapper operation.
Related tests are updated but this PR on its own will not pass premerge
tests. All patches in the stack are needed before it can be compiled and
passes tests.
Commit: f6d431f208c0fa48827eac40e7acf788346a9967
https://github.com/llvm/llvm-project/commit/f6d431f208c0fa48827eac40e7acf788346a9967
Author: Xu Zhang <simonzgx at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/CodeGenCommonISel.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
M llvm/lib/Target/ARM/MVEVPTBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/lib/Target/X86/X86CmovConversion.cpp
M llvm/lib/Target/X86/X86FixupSetCC.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
Log Message:
-----------
[CodeGen] Make the parameter TRI required in some functions. (#85968)
Fixes #82659
There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411.
Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.
After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.
Commit: 4c16b1231cc78cc6271cff5ab33f799cd437ac31
https://github.com/llvm/llvm-project/commit/4c16b1231cc78cc6271cff5ab33f799cd437ac31
Author: Hans Wennborg <hans at chromium.org>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroInstr.h
Log Message:
-----------
[coro] Tweak comments about CoroAwaitSuspendInst
to reflect that there are three variants.
Commit: 1465299092c647fdb484235cc864826dca36f308
https://github.com/llvm/llvm-project/commit/1465299092c647fdb484235cc864826dca36f308
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
Log Message:
-----------
[MLIR][OpenMP] Update op verifiers dependent on omp.wsloop (2/5) (#89211)
This patch updates verifiers for `omp.ordered`, `omp.ordered.region`,
`omp.cancel` and `omp.cancellation_point`, which check for a parent
`omp.wsloop`.
After transitioning to a loop wrapper-based approach, the expected
direct parent will become `omp.loop_nest` instead, so verifiers need to
take this into account.
This PR on its own will not pass premerge tests. All patches in the
stack are needed before it can be compiled and passes tests.
Commit: 8843d541b6640ec8928cfda835ff22a657656037
https://github.com/llvm/llvm-project/commit/8843d541b6640ec8928cfda835ff22a657656037
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/test/Conversion/SCFToOpenMP/reductions.mlir
M mlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir
Log Message:
-----------
[MLIR][SCF] Update scf.parallel lowering to OpenMP (3/5) (#89212)
This patch makes changes to the `scf.parallel` to `omp.parallel` +
`omp.wsloop` lowering pass in order to introduce a nested
`omp.loop_nest` as well, and to follow the new loop wrapper role for
`omp.wsloop`.
This PR on its own will not pass premerge tests. All patches in the
stack are needed before it can be compiled and passes tests.
Commit: 2e37f28f3bac768465e9112caf88e9370a62234d
https://github.com/llvm/llvm-project/commit/2e37f28f3bac768465e9112caf88e9370a62234d
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
M mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir
M mlir/test/Target/LLVMIR/omptarget-wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-data-target-device.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-nested.mlir
M mlir/test/Target/LLVMIR/openmp-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir
Log Message:
-----------
[MLIR][OpenMP] Update omp.wsloop translation to LLVM IR (4/5) (#89214)
This patch introduces minimal changes to the MLIR to LLVM IR translation
of `omp.wsloop` to support the loop wrapper approach.
There is `omp.loop_nest` related translation code that should be
extracted and shared among all loop operations (e.g. `omp.simd`). This
would possibly also help in the addition of support for compound
constructs later on. This first approach is only intended to keep things
running after the transition to loop wrappers and not to add support for
other use cases enabled by that transition.
This PR on its own will not pass premerge tests. All patches in the
stack are needed before it can be compiled and passes tests.
Commit: ca4dbc271842e8c9b5ed01bd66b687ab703896d0
https://github.com/llvm/llvm-project/commit/ca4dbc271842e8c9b5ed01bd66b687ab703896d0
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Lower/OpenMP/FIR/copyin.f90
M flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90
M flang/test/Lower/OpenMP/FIR/location.f90
M flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90
M flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90
M flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90
M flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/FIR/target.f90
M flang/test/Lower/OpenMP/FIR/unstructured.f90
M flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90
M flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90
M flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90
M flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90
M flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/FIR/wsloop-simd.f90
M flang/test/Lower/OpenMP/FIR/wsloop-variable.f90
M flang/test/Lower/OpenMP/FIR/wsloop.f90
M flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90
M flang/test/Lower/OpenMP/copyin.f90
M flang/test/Lower/OpenMP/default-clause-byref.f90
M flang/test/Lower/OpenMP/default-clause.f90
M flang/test/Lower/OpenMP/hlfir-wsloop.f90
M flang/test/Lower/OpenMP/lastprivate-commonblock.f90
M flang/test/Lower/OpenMP/lastprivate-iv.f90
M flang/test/Lower/OpenMP/location.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90
M flang/test/Lower/OpenMP/parallel-wsloop.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-chunks.f90
M flang/test/Lower/OpenMP/wsloop-collapse.f90
M flang/test/Lower/OpenMP/wsloop-monotonic.f90
M flang/test/Lower/OpenMP/wsloop-nonmonotonic.f90
M flang/test/Lower/OpenMP/wsloop-ordered.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multi.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/OpenMP/wsloop.f90
Log Message:
-----------
[Flang][OpenMP][Lower] Update workshare-loop lowering (5/5) (#89215)
This patch updates lowering from PFT to MLIR of workshare loops to
follow the loop wrapper approach. Unit tests impacted by this change are
also updated.
As the last patch of the stack, this should compile and pass unit tests.
Commit: 3328ccf68985ed512d448890ee900ed5f4bdb620
https://github.com/llvm/llvm-project/commit/3328ccf68985ed512d448890ee900ed5f4bdb620
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/shape.f90
Log Message:
-----------
[flang] lower SHAPE intrinsic (#89785)
Semantics usually fold SHAPE into an array constructor, but sometimes it
cannot (like when the source is a function result that cannot be
duplicated in expression analysis). Add lowering handling for shape.
Commit: 96b2e35a58819eb2fbe1821650e35a1f0e085bd7
https://github.com/llvm/llvm-project/commit/96b2e35a58819eb2fbe1821650e35a1f0e085bd7
Author: David Sherwood <57997763+david-arm at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
Log Message:
-----------
[CostModel][AArch64] Improve fixed-width vector costs for get.active.lane.mask (#89068)
When SVE is available we can lower calls to get.active.lane.mask using
the SVE whilelo instruction, however in practice since vXi1 types are
not legal for NEON we often end up expanding the predicate into a vector
of integers, e.g. v4i1 -> v4i32. This usually happens when we have to
keep the predicate live out of the block, for example when the predicate
is the incoming value to a PHI node in a tail-folded vector loop.
Currently in such cases the intrinsic call has a cost of 1, which is far
too low when considering the extra instructions required to expand the
predicate. This patch fixes that by basing the cost on the number of
lane moves required for expansion. This is required for a follow-on
patch that adds the cost of the intrinsic call to the vectorisation cost
model, so that we can teach the vectoriser to make better choices.
Commit: e58dcf135f3a6e453e7b123642675e39b8527f2d
https://github.com/llvm/llvm-project/commit/e58dcf135f3a6e453e7b123642675e39b8527f2d
Author: smanna12 <soumi.manna at intel.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Log Message:
-----------
[Clang] [NFC] Prevent null pointer dereference in Sema::InstantiateFunctionDefinition (#89801)
In the lambda function within
clang::Sema::InstantiateFunctionDefinition, the return value of a
function that may return null is now checked before dereferencing to
avoid potential null pointer dereference issues which can lead to
crashes or undefined behavior in the program.
Commit: a04714701f17663e3e9879a50ed07bbb421ca209
https://github.com/llvm/llvm-project/commit/a04714701f17663e3e9879a50ed07bbb421ca209
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
Log Message:
-----------
[AMDGPU] Add a trap lowering workaround for gfx11 (#85854)
On gfx11 shaders run with PRIV=1, which causes `s_trap 2` to be treated
as a nop, which means it isn't a correct lowering for the trap
intrinsic. As a workaround, this commit instead lowers the trap
intrinsic to instructions that simulate the behavior of s_trap 2.
Fixes: SWDEV-438421
Commit: 21ef187654c819fd097171afcc6c9855dccdb36d
https://github.com/llvm/llvm-project/commit/21ef187654c819fd097171afcc6c9855dccdb36d
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/unittests/IR/IntrinsicsTest.cpp
Log Message:
-----------
[PGO] Test for inheritance relationships for `instrprof` intrinsics (#89485)
Commit: 50082d64e633b9baa918a209fc9105aa330b89fa
https://github.com/llvm/llvm-project/commit/50082d64e633b9baa918a209fc9105aa330b89fa
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
Log Message:
-----------
DAG: Fix widening of fptrunc_round vectors (#89918)
Commit: e1aa16299f626317068c3d99e035d447145353c7
https://github.com/llvm/llvm-project/commit/e1aa16299f626317068c3d99e035d447145353c7
Author: yingopq <115543042+yingopq at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsExpandPseudo.cpp
M llvm/test/CodeGen/Mips/atomic-min-max.ll
Log Message:
-----------
[Mips] Use ANDi in for zero-extend in subword atomic umax/umin for both r2 and pre-R2 (#89881)
About unsigned max/min, ANDi is available for all ISA revisions in
extend before slt insn.
So that we can reduce one instruction.
Commit: a682f528d4d2523c044ab08cf3a8ecfd8e42760d
https://github.com/llvm/llvm-project/commit/a682f528d4d2523c044ab08cf3a8ecfd8e42760d
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp
Log Message:
-----------
[IR][test] Fix warning in MMRA tests
Commit: 418bdb49a758a5b3a128781a819b4e160521b7ed
https://github.com/llvm/llvm-project/commit/418bdb49a758a5b3a128781a819b4e160521b7ed
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
Log Message:
-----------
[clang][RISCV] Remove LMUL=8 scalar input for some vector crypto instructions (#89867)
Since the requirement is EEW=32, it's impossible that EGW=128
needs LMUL=8.
Commit: a38f201f1ec70c2b1f3cf46e7f291c53bb16753e
https://github.com/llvm/llvm-project/commit/a38f201f1ec70c2b1f3cf46e7f291c53bb16753e
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/cmake/caches/Release.cmake
Log Message:
-----------
[CMake][Release] Add stage2-package target (#89517)
This target will be used to generate the release binary package for
uploading to GitHub.
Commit: b4f923e9124c5ec0619a962deb386dd9b52a29be
https://github.com/llvm/llvm-project/commit/b4f923e9124c5ec0619a962deb386dd9b52a29be
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
Log Message:
-----------
[RISCV] Strength reduce mul by 2^M - 3/5/9 (#88993)
We can expand these as the three instruction sequence: (sub (shl X, C1), (shXadd X, x)).
Commit: c1d00510ab5e7f5052efb1e678173e3a97302e61
https://github.com/llvm/llvm-project/commit/c1d00510ab5e7f5052efb1e678173e3a97302e61
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll
Log Message:
-----------
[Inline][Cloning] Introduce test for PR87963 (NFC)
Commit: a61f9fe31750cee65c726fb51f1b14e31e177258
https://github.com/llvm/llvm-project/commit/a61f9fe31750cee65c726fb51f1b14e31e177258
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll
M llvm/test/Transforms/Inline/prof-update-sample-alwaysinline.ll
M llvm/test/Transforms/Inline/prof-update-sample.ll
Log Message:
-----------
[Inline][Cloning] Defer simplification after phi-nodes resolution
A logic issue arose when inlining via `CloneAndPruneFunctionInto`,
which, besides cloning, performs instruction simplification as well.
By the time a new cloned instruction is being simplified, phi-nodes
are not remapped yet as the whole CFG needs to be processed first.
As `VMap` state at this stage is incomplete, `threadCmpOverPHI` and
variants could lead to unsound optimizations. This issue has been
addressed by performing basic constant folding while cloning, and
postponing instruction simplification once phi-nodes are revisited.
Fixes: https://github.com/llvm/llvm-project/issues/87534.
Commit: e0adf63afc33a1e7fd4494c4f327d5ee4082b393
https://github.com/llvm/llvm-project/commit/e0adf63afc33a1e7fd4494c4f327d5ee4082b393
Author: Alexander M <iammorjj at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M lldb/CMakeLists.txt
Log Message:
-----------
[lldb] fix python extension debug suffix on Win (#89037)
ae389b2450bd604a3f3bbe5b09b333b2d99801dd change doesn't cover "_d"
suffix for Debug build on Windows.
Fixed #87381.
Commit: fb302b19443ceb5a79628bb0f83383a3e96a4b74
https://github.com/llvm/llvm-project/commit/fb302b19443ceb5a79628bb0f83383a3e96a4b74
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir
R mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir
Log Message:
-----------
[mlir][ArmSME] Move tests out of `vector-ops-to-llvm.mlir` (#89905)
These tests basically were integration tests as unit tests, checking too
many passes at once to be useful, and brittle to any changes.
This patch moves (non-duplicated) tests to `vector-to-arm-sme.mlir`
(which only tests `-convert-vector-to-arm-sme`). The lowering after
that e.g. `ArmSME -> SCF` and `ArmSME -> LLVM` already have their
own set of tests covering these cases.
Commit: fc13353e10b443101b7304c5f90d70a06e20e589
https://github.com/llvm/llvm-project/commit/fc13353e10b443101b7304c5f90d70a06e20e589
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
Log Message:
-----------
Revert "[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)"
Seems to cause an address sanitizer failure on one of the buildbots related
to live intervals.
Commit: cd3e71fb7a5fed9a7e5ee54a2f956ce33b90b90c
https://github.com/llvm/llvm-project/commit/cd3e71fb7a5fed9a7e5ee54a2f956ce33b90b90c
Author: Mike Rice <michael.p.rice at intel.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
Log Message:
-----------
[NFC][clang][analyzer] Initialize pointer field in StreamOperationEvaluator (#89837)
Add an initializer for StreamSym, which is a pointer. The pointers in
this class are set in the Init function, but all should be initialized
in the constructor to avoid confusion and static verifier hits.
Commit: 3abcd5f282fd17be679fa1775154672feead4ead
https://github.com/llvm/llvm-project/commit/3abcd5f282fd17be679fa1775154672feead4ead
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp
A flang/test/Lower/OpenMP/function-filtering-3.f90
Log Message:
-----------
[flang][openmp] fix OMPFunctionFiltering pass after #87796 (#89776)
The pass assumed that all fun.func symbol usages could be safely
replaced by undef, that is not true after #87796 that added a back link
from internal procedure back to the parent procedure. This caused the
internal procedures to be erased and then processed (segfault).
Also set visibility of such internal procedures so that MLIR do not remove them before
the target function is generated for the target region.
Commit: f489043826b25af7afa9f95faa0c301bd55681a2
https://github.com/llvm/llvm-project/commit/f489043826b25af7afa9f95faa0c301bd55681a2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/TargetParser/RISCVISAInfo.cpp
Log Message:
-----------
[RISCV] Sort the ImpliedExts tables in RISCVISAInfo.cpp alphabetically. NFC
Commit: 31e769cfadf0bd99a990508600ef5bfeaaf44b0d
https://github.com/llvm/llvm-project/commit/31e769cfadf0bd99a990508600ef5bfeaaf44b0d
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M libcxx/include/__numeric/saturation_arithmetic.h
Log Message:
-----------
[libc++] Makes saturation functions privately available. (#89503)
These functions are useful in the implementation of the time zone
database. So expose them with private names.
The functions could be exposed before C++ 20, but since libc++ is mostly
C++ 17 complete it seems less useful to allow earlier.
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 7c0da7993ecfffe1396a15383eb357fa624265af
https://github.com/llvm/llvm-project/commit/7c0da7993ecfffe1396a15383eb357fa624265af
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/include/flang/Lower/Allocatable.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/OpenACC/acc-declare.f90
Log Message:
-----------
[flang][cuda] Use fir.cuda_deallocate for automatic deallocation (#89662)
Automatic deallocation of allocatable that are cuda device variable must
use the fir.cuda_deallocate operation. This patch update the automatic
deallocation code generation to use this operation when the variable is
a cuda variable.
This patch has also the side effect to correctly call
`attachDeclarePostDeallocAction` for OpenACC declare variable on
automatic deallocation as well. Update the code in
`attachDeclarePostDeallocAction` so we do not attach on fir.result but
on the correct last op.
Commit: d3f6a88a1fb36f94c71940514e576821c6cc3ade
https://github.com/llvm/llvm-project/commit/d3f6a88a1fb36f94c71940514e576821c6cc3ade
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll
Log Message:
-----------
[AArch64] Unify lowering logic for fixed-length vectors. (#89393)
In preparation of decoupling codegen for SME from SVE, this patch does a
bit of cleanup to unify the logic around calling
'addTypeForFixedLengthSVE'.
We only want to call this function when:
* We have access to both SVE and NEON, but we prefer to use SVE.
* We have access to SVE, but there is no access to NEON.
Inside 'addTypeForFixedLengthSVE', we normally use Custom lowering for
all operations so they can be converted to/from scalable vector
operations.
However, there are some exceptions:
* For 64/128bit vector loads/stores we prefer the AdvSIMD LDR/STR
D/Q-reg instructions, since these are available in Streaming-SVE mode.
* For some operations like gather/scatter, we can only use SVE if the
full set of SVE instructions is available (as opposed to the
streaming[-compatible] subset). Otherwise, these operations need to
expand (scalarise)
Commit: b10e4b82e624af870c2a03ce0c5515148136e287
https://github.com/llvm/llvm-project/commit/b10e4b82e624af870c2a03ce0c5515148136e287
Author: Usman Nadeem <mnadeem at quicinc.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/test/Transforms/GVN/condprop.ll
M llvm/unittests/Analysis/LoadsTest.cpp
Log Message:
-----------
[GVN] Restrict equality propagation for pointers (#82458)
This patch does the following:
Adds the following functions:
- replaceDominatedUsesWithIf() that takes a callback.
- canReplacePointersIfEqual(...) returns true if the underlying object
is the same, and for null and const dereferencable pointer replacements.
- canReplacePointersIfEqualInUse(...) returns true for the above as well
as if the use is in icmp/ptrtoint or phi/selects feeding into them.
Updates GVN using the functions above so that the pointer replacements
are only made using the above API.
https://reviews.llvm.org/D143129
Commit: d609029d6c9aae84b52238f39c35200316bdbb93
https://github.com/llvm/llvm-project/commit/d609029d6c9aae84b52238f39c35200316bdbb93
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/include/clang/Lex/HeaderSearch.h
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/prune-non-affecting-module-map-files-textual.c
Log Message:
-----------
[clang][modules] Allow module maps with textual headers to be non-affecting (#89441)
When writing out a PCM, we skip serializing headers' `HeaderFileInfo`
struct whenever this condition evaluates to `true`:
```c++
!HFI || (HFI->isModuleHeader && !HFI->isCompilingModuleHeader)
```
However, when Clang parses a module map file, each textual header gets a
`HFI` with `isModuleHeader=false`, `isTextualModuleHeader=true` and
`isCompilingModuleHeader=false`. This means the condition evaluates to
`false` even if the header was never included and the module map did not
affect the compilation. Each PCM file that happened to parse such module
map then contains a copy of the `HeaderFileInfo` struct for all textual
headers, and considers the containing module map affecting.
This patch makes it so that we skip headers that have not been included,
essentially removing the virality of textual headers when it comes to
PCM serialization.
Commit: 84bc21f9101730af611a0175d89ae2056d5f41a7
https://github.com/llvm/llvm-project/commit/84bc21f9101730af611a0175d89ae2056d5f41a7
Author: Brian Gesiak <brian at modocache.io>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/unittests/CMakeLists.txt
A mlir/unittests/Tools/CMakeLists.txt
A mlir/unittests/Tools/lsp-server-support/CMakeLists.txt
A mlir/unittests/Tools/lsp-server-support/Transport.cpp
Log Message:
-----------
[mlir-lsp] Add transport unit tests (#89855)
Add unit tests for some aspects of the JSON transport and message
handler. These will be expanded in future patches as behavior is
modified.
Commit: 12d47247e5046b959af180e12f648c54e2c5e863
https://github.com/llvm/llvm-project/commit/12d47247e5046b959af180e12f648c54e2c5e863
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
Log Message:
-----------
[RISCV][NFC] Move RISCVMaskedPseudoTable to RISCVInstrInfo
Commit: cdc3931f085b6b57da997b1d8c88be49a06c9f45
https://github.com/llvm/llvm-project/commit/cdc3931f085b6b57da997b1d8c88be49a06c9f45
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
Log Message:
-----------
[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc
Commit: 80f510bbc9561324fc13bac22aad2e3ef47a59c5
https://github.com/llvm/llvm-project/commit/80f510bbc9561324fc13bac22aad2e3ef47a59c5
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[RISCV] Use lookup tables to find CVTFOpc
Commit: af82d01fbbce7808605f3a8b22dd1ca7fdec7886
https://github.com/llvm/llvm-project/commit/af82d01fbbce7808605f3a8b22dd1ca7fdec7886
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
Log Message:
-----------
Reapply "[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)"
The original commit was calling shrinkToUses on an interval for a virtual
register whose def was erased. This fixes it by calling shrinkToUses first
and removing the interval if we erase the old VL def.
Commit: 286bd42a7a799e3d9035c09bf0d64cb1a1eef682
https://github.com/llvm/llvm-project/commit/286bd42a7a799e3d9035c09bf0d64cb1a1eef682
Author: Jorn Tuyls <jtuyls at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir/Dialect/SCF/Transforms/Passes.h
M mlir/include/mlir/Dialect/SCF/Transforms/Passes.td
M mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SCF/Transforms/ForallToFor.cpp
A mlir/test/Dialect/SCF/forall-to-for.mlir
Log Message:
-----------
[mlir] Extract forall_to_for logic into reusable function and add pass (#89636)
This PR extracts the existing `scf.forall` to `scf.for` conversion logic
inside a transform op (https://github.com/llvm/llvm-project/pull/65474)
into a standalone function which can be used in other transformations
and adds a `scf-forall-to-for` pass.
Commit: 8350d9c23d76fb95f42674a1563cbe8c32582dd5
https://github.com/llvm/llvm-project/commit/8350d9c23d76fb95f42674a1563cbe8c32582dd5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/MC/RISCV/rv32dc-valid.s
M llvm/test/MC/RISCV/rv32fc-valid.s
M llvm/test/MC/RISCV/rv64dc-valid.s
Log Message:
-----------
[RISCV] Sync RISCVFeatures.td implies list with RISCVISAInfo.cpp.
This makes Zcf imply F and Zcd imply D in RISCVFeatures.td. They
were already implied in RISCISAInfo.cpp.
Some test RUN lines had to be removed because they were testing
that Zcf without F or Zcd without D would reject some instructions.
Commit: a45eb628779562fac72366f594fbcdc5607b4f8d
https://github.com/llvm/llvm-project/commit/a45eb628779562fac72366f594fbcdc5607b4f8d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
Log Message:
-----------
AtomicExpand: Fix dropping a syncscope when bitcasting atomicrmw
Commit: fd9273593390c4e5004bba27eeeea60e44175dcf
https://github.com/llvm/llvm-project/commit/fd9273593390c4e5004bba27eeeea60e44175dcf
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/docs/Tutorials/UnderstandingTheIRStructure.md
Log Message:
-----------
[MLIR][Doc] Fix NamedAttribute API in code sample (NFC)
Commit: 744d469500d209b7bf548d81f607d61a156db2e6
https://github.com/llvm/llvm-project/commit/744d469500d209b7bf548d81f607d61a156db2e6
Author: Thurston Dang <thurston at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
M llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
M llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
Log Message:
-----------
[hwasan] Optimize outlined memaccess for fixed shadow on Aarch64 (#88544)
The HWASan transform currently always uses x20 to pass the shadow base to hwasan_check_memaccess_shortgranules, even if the shadow base is a constant known at compile time (e.g., for Fuchsia, KHWASan, or via -hwasan-mapping-offset). This patch uses the fixed shadow variant of the hwasan_check_memaccess_shortgranules intrinsic (introduced in https://github.com/llvm/llvm-project/commit/365bddf634993d5ea357e9715d8aacd7ee40c4b5), allowing the shadow base to be materialized inside the memaccess callee.
We currently only support this optimization for AArch64; it is a no-op on other platforms due to lack of support for lowering the intrinsic.
Note: when a binary is instrumented with -hwasan-mapping-offset, it is necessary to specify HWASAN_OPTIONS=fixed_shadow_base=... (see ea991a11b2a3d2bfa545adbefb71cd17e8970a43) at runtime to ensure the shadow is mapped appropriately.
Commit: 69a3976e427d95eca3670cac963088c76612c9db
https://github.com/llvm/llvm-project/commit/69a3976e427d95eca3670cac963088c76612c9db
Author: Scott Linder <Scott.Linder at amd.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
Log Message:
-----------
[AMDGPU][NFC] Fix typo in HeterogeneousDWARF doc
Commit: ff57f40673f0db2c1a867e5697d5407bc9f39a5e
https://github.com/llvm/llvm-project/commit/ff57f40673f0db2c1a867e5697d5407bc9f39a5e
Author: Oleksandr "Alex" Zinenko <zinenko at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/python/mlir/dialects/transform/interpreter/__init__.py
M mlir/test/python/dialects/transform_interpreter.py
Log Message:
-----------
[mlir][py] fix option passing in transform interpreter (#89922)
There was a typo in dispatch trampoline.
Commit: b8f3024a315074e0f880542c33cb89681eebc5a3
https://github.com/llvm/llvm-project/commit/b8f3024a315074e0f880542c33cb89681eebc5a3
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
M clang/test/CodeGen/builtins-wasm.c
M clang/test/CodeGen/ms-intrinsics-other.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGenOpenCL/builtins-generic-amdgcn.cl
M clang/test/Headers/wasm.c
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/InstrTypes.h
M llvm/lib/IR/Attributes.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstCombine/bit_floor.ll
M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
M llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll
M llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll
M llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll
M llvm/test/Transforms/InstCombine/ctpop-cttz.ll
M llvm/test/Transforms/InstCombine/ctpop-pow2.ll
M llvm/test/Transforms/InstCombine/ctpop.ll
M llvm/test/Transforms/InstCombine/cttz-abs.ll
M llvm/test/Transforms/InstCombine/cttz-negative.ll
M llvm/test/Transforms/InstCombine/cttz.ll
M llvm/test/Transforms/InstCombine/ffs-1.ll
M llvm/test/Transforms/InstCombine/ffs-i16.ll
M llvm/test/Transforms/InstCombine/fls-i16.ll
M llvm/test/Transforms/InstCombine/fls.ll
M llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
M llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll
M llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
M llvm/test/Transforms/InstCombine/freeze.ll
M llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
M llvm/test/Transforms/InstCombine/intrinsic-select.ll
M llvm/test/Transforms/InstCombine/intrinsics.ll
M llvm/test/Transforms/InstCombine/ispow2.ll
M llvm/test/Transforms/InstCombine/known-non-zero.ll
M llvm/test/Transforms/InstCombine/known-phi-recurse.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll
M llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
M llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
M llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/sext.ll
M llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/sub-xor.ll
M llvm/test/Transforms/InstCombine/xor.ll
M llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
M llvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll
Log Message:
-----------
[InstCombine] Swap out range metadata to range attribute for cttz/ctlz/ctpop (#88776)
Since all optimizations that use range metadata now also handle range attribute, this patch replaces writes of
range metadata for call instructions to range attributes.
Commit: 2e770edd8ce13f48402f1d93e5fb982d8a2ebe64
https://github.com/llvm/llvm-project/commit/2e770edd8ce13f48402f1d93e5fb982d8a2ebe64
Author: Sebastian Poeplau <poeplau at adacore.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/tools/c-index-test/c-index-test.c
M clang/tools/libclang/CXSourceLocation.cpp
M clang/unittests/libclang/LibclangTest.cpp
Log Message:
-----------
[libclang] Compute the right spelling location (#72400)
Locations inside macro expansions have different spelling/expansion
locations. Apply a FIXME to make the libclang function
clang_getSpellingLocation return the right spelling location, and adapt
the testsuite driver code to use the file location rather than the
spelling location to compute source ranges.
Co-authored-by: Matthieu Eyraud <eyraud at adacore.com>
Commit: 57f0284efc74dfad7a3ff20e2cf1f74a70a08824
https://github.com/llvm/llvm-project/commit/57f0284efc74dfad7a3ff20e2cf1f74a70a08824
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel] Mark linux LLDB plugin as linux only (#89961)
Otherwise if you bazel build //... on macOS this fails to build
Commit: 3c2e614acd76495fda74f945dddd8bb89ae0f41f
https://github.com/llvm/llvm-project/commit/3c2e614acd76495fda74f945dddd8bb89ae0f41f
Author: Troy Butler <118708570+Troy-Butler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
Log Message:
-----------
[llvm][AArch64] Add missing default cases (#89930)
Addresses issue #89709.
Functions getAUTOpcodeForKey() and getPACOpcodeForKey() contain switch
statements without default cases. Resolved by adding a call to
llvm_unreachable() at the end of each function.
---------
Signed-off-by: Troy-Butler <squintik at outlook.com>
Co-authored-by: Troy-Butler <squintik at outlook.com>
Commit: 0e57c3eb0dbfe2929ab899b2409807402acfc38e
https://github.com/llvm/llvm-project/commit/0e57c3eb0dbfe2929ab899b2409807402acfc38e
Author: Andy Kaylor <andrew.kaylor at intel.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/test/Driver/fast-math.c
Log Message:
-----------
Clean up the checks in the fast-math driver test
This change replaces most of the cc1 option checks in the driver test for fast-math option handling. These changes rely on the assumption that the order in which the driver emits floating-point options is stable.
The changes also rely on the assumption that the order of prefixes listed on the FileCheck command line is unimportant and that all prefixed checks will be combined and checked as if they were a single prefix. At the time of the change, that worked.
Commit: 3f29228a10e65eadc23ccd40dc8fbe1efe268892
https://github.com/llvm/llvm-project/commit/3f29228a10e65eadc23ccd40dc8fbe1efe268892
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M libcxx/benchmarks/CMakeLists.txt
A libcxx/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
Log Message:
-----------
[libc++][format] Adds an escaped output benchmark. (#88020)
This is a preparation to measure the performance impact of
- P2713R1 Escaping improvements in std::format
and its performance improving followup patch.
Commit: 007e859258540cef0dcb1f0a1bdd9e74111f9ba0
https://github.com/llvm/llvm-project/commit/007e859258540cef0dcb1f0a1bdd9e74111f9ba0
Author: Abhinav Garg <39309352+abhigargrepo at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
A llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
Log Message:
-----------
AMDGPU: Pre-commit test to verify mode change in fp constrained operations (#88858)
This test will check the mode register in case of constrained floating
point operations.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: d421a6c9ef1dd286832fce3b4f955d4ba99ce192
https://github.com/llvm/llvm-project/commit/d421a6c9ef1dd286832fce3b4f955d4ba99ce192
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
R flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
Log Message:
-----------
[flang][driver] Remove `flang -help` tests (#89504)
These tests were introduced when the Flang driver was originally
incepted. Back then, `flang-new` only supported a handful of basic
options (e.g. `-v`, `-help`, `-E`) and those `-help` tests were used to
guard against Clang options "leaking" into `flang-new -help`.
With the introduction of the concept of "visibility" (see
https://reviews.llvm.org/D157837 and https://reviews.llvm.org/D157151),
these tests are effectively redundant. Also, with the number of flags
growing, these tests are getting rather brittle.
Commit: 2575cd8a900283368e451cdbc27a2e4db0722af9
https://github.com/llvm/llvm-project/commit/2575cd8a900283368e451cdbc27a2e4db0722af9
Author: Andy Kaylor <andrew.kaylor at intel.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
Add ics link for Floating Point WG (#82545)
This adds a link to an ics file for the LLVM Floating Point WG line in
the Getting Involved page.
Commit: 57794835279669358ff2828d659eb7133fc0e4bf
https://github.com/llvm/llvm-project/commit/57794835279669358ff2828d659eb7133fc0e4bf
Author: Alex Langford <alangford at apple.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ThreadedCommunication.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Target/TargetList.h
M lldb/include/lldb/Target/Thread.h
M lldb/include/lldb/Utility/Broadcaster.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBCommunication.cpp
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBEvent.cpp
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/API/SBThread.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ThreadedCommunication.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetList.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Utility/Broadcaster.cpp
Log Message:
-----------
[lldb][nfc] Move broadcaster class strings away from ConstString (#89690)
These are hardcoded strings that are already present in the data section
of the binary, no need to immediately place them in the ConstString
StringPools. Lots of code still calls `GetBroadcasterClass` and places
the return value into a ConstString. Changing that would be a good
follow-up.
Additionally, calls to these functions are still wrapped in ConstStrings
at the SBAPI layer. This is because we must guarantee the lifetime of
all strings handed out publicly.
Commit: 37e13d4924841bd84edb8c67c667d6d2a6c2bc63
https://github.com/llvm/llvm-project/commit/37e13d4924841bd84edb8c67c667d6d2a6c2bc63
Author: Brian Gesiak <brian at modocache.io>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir/Tools/lsp-server-support/Transport.h
M mlir/unittests/Tools/lsp-server-support/Transport.cpp
Log Message:
-----------
[mlir-lsp] Log invalid notification params (#89856)
When the `lsp::MessageHandler` processes a request with invalid params
(that is, the "params" JSON sent along with the request does not match
the shape expected by the message handler for the given method), it
replies by sending an error response to the client.
On the other hand, the language server protocol specifies that
notifications must not result in responses. As a result, when the
JSON params accompanying a notification cannot be parsed, no error is
sent back; there is no indication that an error has occurred at all.
This patch adds an error log for that case. Although clients cannot
parse error logs, this at least provides an indication that something
went wrong on the language server side.
Commit: 791161516f48f41ae90f1231fdfc7374f43b5a9f
https://github.com/llvm/llvm-project/commit/791161516f48f41ae90f1231fdfc7374f43b5a9f
Author: Frederic Cambus <fred at statdns.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M compiler-rt/lib/fuzzer/build.sh
Log Message:
-----------
[compiler-rt] Update libFuzzer build script to use C++17. (#89604)
libFuzzer uses std::clamp which was introduced in C++17.
Commit: 03bb10dfb3725ec2c31fb66deede96d066f2b49a
https://github.com/llvm/llvm-project/commit/03bb10dfb3725ec2c31fb66deede96d066f2b49a
Author: Chao Chen <116223022+chencha3 at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
Log Message:
-----------
[MLIR][XeGPU] Add dpas, atomic, and named barrier ops (#88973)
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Co-authored-by: Adam Siemieniuk <adam.siemieniuk at intel.com>
Commit: fc538b070de69315fe05105e8c0bc622fb61168a
https://github.com/llvm/llvm-project/commit/fc538b070de69315fe05105e8c0bc622fb61168a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Pass SDVTList instead of VTs to *SDNode constructors. NFC (#89880)
All of these constructors were creating a SDVTList using an EVT* created
by SDNode::getValueTypeList. This EVT needs to live at least as long as
the SDNode that uses it. To do this, SDNode::getValueTypeList contains
several function scoped static variables that hold the memory for the
EVT. So the EVT lives until global destructors run.
This is problematic since an EVT contains a Type* that points to memory
allocated by an LLVMContext. If multiple LLVMContexts are used that
don't have overlapping lifetimes, we can end up with stale or or
incorrect pointers cached in the EVTs owned by SDNode::getValueTypeList.
I want to try to make the EVTs be owned by SelectionDAG instead. This is
already done for SDVTLists with more than 1 VT. The single value case is
a very old optimizaton that should be re-evaluated. In order to do this,
I need the SDVTLists to be created by SelectionDAG rather than by the
SDNode itself.
This patch doesn't change how the allocation is done yet. It just moves
the code around.
This patch does reduce the number of calls to getVTList since we now
share with the call needed for the SDNode FoldingSet.
Part of fixing #88233.
Commit: 712d7dba4f27a1990241e02435d765a5a3808aea
https://github.com/llvm/llvm-project/commit/712d7dba4f27a1990241e02435d765a5a3808aea
Author: Bill Wendling <5993918+bwendling at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
[Clang] Improve testing for the flexible array member (#89462)
Testing for the name of the flexible array member isn't as robust as
testing the FieldDecl pointers.
Commit: f3f6f22dfcced21116710a477c78e0739c942139
https://github.com/llvm/llvm-project/commit/f3f6f22dfcced21116710a477c78e0739c942139
Author: Brian Gesiak <brian at modocache.io>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Tools/lsp-server-support/Transport.cpp
Log Message:
-----------
[mlir-lsp] Initialize Reply::method member (#89857)
When debug level logging is enabled (by adding a call to
`Logger::setLogLevel(Logger::Level::Debug)`), the
`TransportInputTest.RequestWithInvalidParams` unit test logs:
```
[18:35:00.565] --> reply:(92)
```
The format string for this log statement is `"--> reply:{0}({1})"`,
where `{0}` is the original request's method name (that is, the method
name of the request being replied to), and `{1}` is the request ID.
However, because the `Reply` class never initializes its `method`
member, `{0}` is always empty. Initializing it results in the (nicer)
log error below:
```
I[18:35:00.565] --> reply:invalid-params-request(92)
```
Because this is only ever logged for now, its not possible to add a test
case for this. Future patches will rely on `method` being initialized,
however, and will add test cases for this path.
Commit: 63b6efeebf3003b075f384742ade189d2ed6b429
https://github.com/llvm/llvm-project/commit/63b6efeebf3003b075f384742ade189d2ed6b429
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp
Log Message:
-----------
[EntryExitInstrumenter] Don't invalidate analyses if no change was made
Commit: 11bd19a7a25b291af61b6c06cb249b567c116d0e
https://github.com/llvm/llvm-project/commit/11bd19a7a25b291af61b6c06cb249b567c116d0e
Author: aniplcc <aniplccode at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M libc/include/assert.h.def
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/assert-macros.h
M libc/test/include/CMakeLists.txt
A libc/test/include/assert_test.cpp
Log Message:
-----------
[libc][assert] define __STDC_VERSION_ASSERT_H__ (#87592)
Fixes #87561
Commit: c5dcb5239e5a3ee68155ba2d09d1fa37ca512cd7
https://github.com/llvm/llvm-project/commit/c5dcb5239e5a3ee68155ba2d09d1fa37ca512cd7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Move GlobalAddressSDNode and AddrSpaceCastSDNode constructors into header. NFC
These constructors are no more complicated than any of the other
*SDNode constructors that are already in the header.
Commit: 13188bcd9f748dee13cf848340833f6eec2d90d4
https://github.com/llvm/llvm-project/commit/13188bcd9f748dee13cf848340833f6eec2d90d4
Author: AtariDreams <gfunni234 at gmail.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
Log Message:
-----------
[GlobalISel]: Simplify udiv lowering by determining known zeros (#89678)
Commit: 96c45a7fa12619c3abd6b81effe4c80f0916b78b
https://github.com/llvm/llvm-project/commit/96c45a7fa12619c3abd6b81effe4c80f0916b78b
Author: Fangrui Song <i at maskray.me>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M lld/test/ELF/mips-eh_frame-pic.s
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/RISCV/fixups-diff.ll
M llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
R llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s
A llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s
M llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s
M llvm/test/MC/ELF/RISCV/gen-dwarf.s
M llvm/test/MC/RISCV/cfi-advance.s
M llvm/test/MC/RISCV/fde-reloc.s
M llvm/test/MC/RISCV/scoped-relaxation.s
Log Message:
-----------
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
Temporary symbols generated for .eh_frame and .debug_line have an empty
name, which appear in .symtab in the presence of RISC-V style linker
relaxation and will not be discarded by ld/objcopy --discard-locals
(-X).
In contrast, GNU assembler's riscv port assigns a fake name ".L0 " (with
a trailing space) to these symbols so that will be discarded by
ld/objcopy --discard-locals.
This patch matches the GNU behavior. Since Clang's RISC-V targets pass
-X to ld, and GNU ld defaults to -X for RISC-V targets, these ".L0 "
symbols will be discarded after linking by default, as expected by
users.
The llvm-symbolizer special case for RISC-V `SF_FormatSpecific` symbols
https://reviews.llvm.org/D98669 needs to be adjusted.
Note: `"":` in assembly currently crashes.
Commit: 7b06ec073d0bd8abad1274d12900a849bd3829c5
https://github.com/llvm/llvm-project/commit/7b06ec073d0bd8abad1274d12900a849bd3829c5
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/ctx_profile/CMakeLists.txt
A compiler-rt/test/ctx_profile/Unit/lit.site.cfg.py.in
M compiler-rt/test/memprof/CMakeLists.txt
A compiler-rt/test/memprof/Unit/lit.site.cfg.py.in
Log Message:
-----------
[compiler-rt] Make sure `memprof` and `ctx_profile` unittests run (#89814)
They weren't run before as part of `check-compiler-rt`.
Verified by adding a `EXPECT_TRUE(false)` in both and observing test failure.
Commit: d4338733e64f0463a22d98140dac5ecb0d381b6b
https://github.com/llvm/llvm-project/commit/d4338733e64f0463a22d98140dac5ecb0d381b6b
Author: Fangrui Song <i at maskray.me>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Target/M68k/M68kISelLowering.cpp
Log Message:
-----------
[M68k] Fix killRegister use
Commit: ea3eeb483fbbe09b9a66ed4c032cc7168f0265dd
https://github.com/llvm/llvm-project/commit/ea3eeb483fbbe09b9a66ed4c032cc7168f0265dd
Author: Peiming Liu <peiming at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
A mlir/test/Dialect/SparseTensor/fuse_sparse_concat_with_extract_slice.mlir
Log Message:
-----------
[mlir][sparse] fuse concat and extract_slice op if possible. (#89825)
Commit: 418e4b0c4ff2bc22dda318fce0293002a22fa76f
https://github.com/llvm/llvm-project/commit/418e4b0c4ff2bc22dda318fce0293002a22fa76f
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/indirect-goto-pie.test
M bolt/test/X86/shrinkwrapping-do-not-pessimize.s
R bolt/test/runtime/X86/Inputs/indirect_goto.c
R bolt/test/runtime/X86/indirect-goto-pie.test
Log Message:
-----------
[BOLT] Detect incorrect update of dynamic relocations (#89681)
When we rewrite dynamic relocations, there could be cases where they
reference code locations inside functions that were rewritten. When this
happens, we need to precisely map old address to a new one. Until we can
reliably perform the mapping, detect such condition and issue an error
refusing to write a broken binary.
Commit: 82a8c1cf35e6794d4d1e56797d58abbed0112ad9
https://github.com/llvm/llvm-project/commit/82a8c1cf35e6794d4d1e56797d58abbed0112ad9
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/include/flang/Runtime/numeric.h
M flang/lib/Evaluate/type.cpp
M flang/runtime/numeric.cpp
Log Message:
-----------
[flang][runtime] Support SELECTED_CHAR_KIND, SELECTED_LOGICAL_KIND (#89691)
Add code to the runtime support library for the SELECTED_CHAR_KIND and
SELECTED_LOGICAL_KIND intrinsic functions. These are usually used with
constant folding in constant expressions, but the are available for use
with dynamic arguments as well.
Lowering support remains to be implemented.
Commit: 186952f0176fda0f73989c2c9335faf26632e112
https://github.com/llvm/llvm-project/commit/186952f0176fda0f73989c2c9335faf26632e112
Author: Chao Chen <116223022+chencha3 at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt
Log Message:
-----------
[MLIR][XeGPU] Fix Bot failure for #88973 (#89991)
Commit: 69bde04230d45f9bb54cc10af1a6d19cf565dd9e
https://github.com/llvm/llvm-project/commit/69bde04230d45f9bb54cc10af1a6d19cf565dd9e
Author: Jeremy Kun <jkun at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
split XeGPU enums into a separate build rule (#89997)
Fixes the bazel build. Note the addition of the Arith dependency created
duplicate arith enum declarations in the two dialects, so it had to be
spit into its own build rule. This matches what the cmake build does for
this dialect.
Commit: 29c98e59cd84ed5c8dde27876779d6b8830ccac5
https://github.com/llvm/llvm-project/commit/29c98e59cd84ed5c8dde27876779d6b8830ccac5
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll
M llvm/test/Transforms/Inline/prof-update-sample-alwaysinline.ll
M llvm/test/Transforms/Inline/prof-update-sample.ll
Log Message:
-----------
Revert "[Inline][Cloning] Defer simplification after phi-nodes resolution" #87963
Reopens #87534.
Breaks multiple bots:
https://lab.llvm.org/buildbot/#/builders/168/builds/20028
https://lab.llvm.org/buildbot/#/builders/74/builds/27773
And reproducer in a61f9fe31750cee65c726fb51f1b14e31e177258.
This reverts commit a61f9fe31750cee65c726fb51f1b14e31e177258.
Commit: c3def59d0f28edf32eb43236db88f21321f36dca
https://github.com/llvm/llvm-project/commit/c3def59d0f28edf32eb43236db88f21321f36dca
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/declarations03.f90
Log Message:
-----------
[flang] Fix bogus error about duplicate binding names (#89786)
Don't call SetBindNameOn() from DeclareUnknownEntity() unless there is
an explicit BIND(C) attribute.
Fixes https://github.com/llvm/llvm-project/issues/89439 and
https://github.com/llvm/llvm-project/issues/89558.
Commit: 1b232fa0e9864dde230db8da82a906c588baf792
https://github.com/llvm/llvm-project/commit/1b232fa0e9864dde230db8da82a906c588baf792
Author: Jeff Niu <jeff at modular.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/cmake/modules/AddMLIR.cmake
M mlir/cmake/modules/CMakeLists.txt
M mlir/cmake/modules/MLIRConfig.cmake.in
M mlir/include/mlir/TableGen/CodeGenHelpers.h
M mlir/lib/TableGen/CodeGenHelpers.cpp
A mlir/test/mlir-tblgen/shard-op-defs.td
A mlir/tools/mlir-src-sharder/CMakeLists.txt
A mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpGenHelpers.cpp
M mlir/tools/mlir-tblgen/OpGenHelpers.h
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/tblgen.bzl
Log Message:
-----------
[mlir][ods] Allow sharding of op definitions (#89423)
Adds an option to `mlir-tblgen -gen-op-defs` `op-shard-count=N` that
divides the
op class definitions and op list into N segments, e.g.
```
// mlir-tblgen -gen-op-defs -op-shard-count=2
void FooDialect::initialize() {
addOperations<
>();
addOperations<
>();
}
```
When split across multiple source files, this can help significantly
improve
dialect compile time for dialects with a large opset.
Commit: ae22ac95354629baca45d979038d73a4ce40d081
https://github.com/llvm/llvm-project/commit/ae22ac95354629baca45d979038d73a4ce40d081
Author: Jeff Niu <jeff at modular.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestDialect.cpp
M mlir/test/lib/Dialect/Test/TestOps.cpp
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[mlir][test] Shard the Test Dialect (NFC) (#89628)
This PR uses the new op sharding mechanism in tablegen to shard the test
dialect's op definitions. This breaks the definition of ops into
multiple source files, speeding up compile time of the test dialect
dramatically. This improves developer cycle times when iterating on the
test dialect.
Commit: 83d06162cca4f35a68e9c64032ba348ac3e27647
https://github.com/llvm/llvm-project/commit/83d06162cca4f35a68e9c64032ba348ac3e27647
Author: Jeff Niu <jeff at modular.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/docs/DefiningDialects/Operations.md
Log Message:
-----------
[mlir][ods] Add documentation on how to use sharded op definitions (NFC) (#89664)
This adds explanations and instructions on how to set up a dialect for
sharded op definitions to the MLIR documentation.
Commit: 0e1bb1d8352ce21808523357d315b73da0d53560
https://github.com/llvm/llvm-project/commit/0e1bb1d8352ce21808523357d315b73da0d53560
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/expression.cpp
A flang/test/Semantics/arg-convert.f90
Log Message:
-----------
[flang] Don't convert actual arguments when interface is implicit (#89795)
When the interface of a procedure is implicit at the point of call,
don't perform actual argument type conversion to the types of the dummy
arguments. This was inadvertently taking place in a case where the
procedure has an implicit interface but was also defined in the same
source file, so that its characteristics were known.
Commit: 68a27989d0c8d58a64dcbb1c78b7002c68a723b2
https://github.com/llvm/llvm-project/commit/68a27989d0c8d58a64dcbb1c78b7002c68a723b2
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Semantics/program-tree.cpp
M flang/lib/Semantics/program-tree.h
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Parser/unrecognized-dir.f90
Log Message:
-----------
[flang] Accept and ignore compiler directives between internal subpro… (#89810)
…grams
The parser only recognizes compiler directives that appear within
internal / module subprograms, not those that might appear between them.
Extend to allow them between subprograms as well.
Commit: 6fd475fe2e7b15a6f6344430d02c454cf8928a35
https://github.com/llvm/llvm-project/commit/6fd475fe2e7b15a6f6344430d02c454cf8928a35
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/runtime/edit-output.cpp
M flang/unittests/Runtime/RuntimeCrashTest.cpp
Log Message:
-----------
[flang][runtime] 'A' output editing for LOGICAL (#89817)
We support 'A' output editing for INTEGER and REAL as an extension; it
turns out to be used as well for LOGICAL in application code.
Commit: fa465b479b09b638e95c8b92ecf358c38910f8b0
https://github.com/llvm/llvm-project/commit/fa465b479b09b638e95c8b92ecf358c38910f8b0
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/runtime/edit-output.cpp
M flang/unittests/Runtime/NumericalFormatTest.cpp
Log Message:
-----------
[flang][runtime] Improve confusing list-directed REAL(2) output (#89846)
List-directed output editing of REAL values will minimize the number of
digits that are emitted by calculating a decimal value that, if read
back in to a REAL variable of the same kind, would compare equal.
This behavior is causing some confusion when applied to list-directed
output of large REAL(2) values. Specifically, the value HUGE(0._2)
(which is 0x7bff in hex) is exactly 65504, but is edited to 65500. by
list-directed output, which selects F0 editing, minimizes the value to
6.55e4, and then formats it without the exponent.
This small patch changes that behavior for cases where the output of
digit-minimized F editing has no digits after the decimal point and
zeroes need to be emitted before it due to the decimal exponent. Digit
minimization is disabled in this case and the exact digits are emitted
instead.
Commit: 8b512e525d3adc56da626a6e4f16c3b2f602aade
https://github.com/llvm/llvm-project/commit/8b512e525d3adc56da626a6e4f16c3b2f602aade
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/docs/Preprocessing.md
M flang/include/flang/Parser/preprocessor.h
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
A flang/test/Preprocessing/backslash-contin1.F90
Log Message:
-----------
[flang][preprocessor] Support \ as line continuation (#89970)
When prescanning a Fortran source file with preprocessing enabled in
free source form, interpret a line-ending backslash as a source line
continuation marker as a C preprocessor would. This usage isn't
completely portable, but it is supported by GNU Fortran and appears in
the source for FPM package manager.
Commit: 14339aba9ca3299f0f76999e0e8f42a7e1eacb10
https://github.com/llvm/llvm-project/commit/14339aba9ca3299f0f76999e0e8f42a7e1eacb10
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M flang/lib/Evaluate/intrinsics.cpp
Log Message:
-----------
[flang] Catch error on REPEAT(x,NCOPIES=array) (#89993)
The NCOPIES= argument to the intrinsic function REPEAT must be a scalar
integer.
Fixes https://github.com/llvm/llvm-project/issues/89851.
Commit: 9961311216f7b22be4fc1221b70ebd1d63bb9843
https://github.com/llvm/llvm-project/commit/9961311216f7b22be4fc1221b70ebd1d63bb9843
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-04-25 (Thu, 25 Apr 2024)
Changed paths:
M lld/test/ELF/mips-eh_frame-pic.s
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/RISCV/fixups-diff.ll
M llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
A llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s
R llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s
M llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s
M llvm/test/MC/ELF/RISCV/gen-dwarf.s
M llvm/test/MC/RISCV/cfi-advance.s
M llvm/test/MC/RISCV/fde-reloc.s
M llvm/test/MC/RISCV/scoped-relaxation.s
Log Message:
-----------
Revert "[MC] Rename temporary symbols of empty name to ".L0 "" (#90002)
Reverts llvm/llvm-project#89693
This broke the premerge bot (bolt tests failing)
Commit: 49586eacd306c70f81986644921e12e55dd7422f
https://github.com/llvm/llvm-project/commit/49586eacd306c70f81986644921e12e55dd7422f
Author: Jeremy Kun <jkun at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
remove duplicate td_library import (#90003)
Reverts bad part of one line from
https://github.com/llvm/llvm-project/commit/ae22ac95354629baca45d979038d73a4ce40d081#diff-9b538219c38ed73e193087a031284f10c62de8692ccc0efbe8c670fe9bfe868f
Commit: a10d67f9fb559d0c35a12b2d26974636bbf642c0
https://github.com/llvm/llvm-project/commit/a10d67f9fb559d0c35a12b2d26974636bbf642c0
Author: Yinying Li <yinyingli at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/SparseTensor.h
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h
M mlir/lib/Bindings/Python/DialectSparseTensor.cpp
M mlir/lib/CAPI/Dialect/SparseTensor.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/test/CAPI/sparse_tensor.c
M mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir
M mlir/test/python/dialects/sparse_tensor/dialect.py
Log Message:
-----------
[mlir][sparse] Enable explicit and implicit value in sparse encoding (#88975)
1. Explicit value means the non-zero value in a sparse tensor. If
explicitVal is set, then all the non-zero values in the tensor have the
same explicit value. The default value Attribute() indicates that it is
not set.
2. Implicit value means the "zero" value in a sparse tensor. If
implicitVal is set, then the "zero" value in the tensor is equal to the
implicit value. For now, we only support `0` as the implicit value but
it could be extended in the future. The default value Attribute()
indicates that the implicit value is `0` (same type as the tensor
element type).
Example:
```
#CSR = #sparse_tensor.encoding<{
map = (d0, d1) -> (d0 : dense, d1 : compressed),
posWidth = 64,
crdWidth = 64,
explicitVal = 1 : i64,
implicitVal = 0 : i64
}>
```
Note: this PR tests that implicitVal could be set to other values as
well. The following PR will add verifier and reject any value that's not
zero for implicitVal.
Commit: 4c8ec8f8bc3fb4dda4fd36c3b2ad745bd3451970
https://github.com/llvm/llvm-project/commit/4c8ec8f8bc3fb4dda4fd36c3b2ad745bd3451970
Author: Kazu Hirata <kazu at google.com>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProfWriter.h
M llvm/include/llvm/ProfileData/MemProf.h
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/test/tools/llvm-profdata/memprof-merge-v0.test
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
Log Message:
-----------
[memprof] Reduce schema for Version2 (#89876)
Curently, the compiler only uses several fields of MemoryInfoBlock.
Serializing all fields into the indexed MemProf file simply wastes
storage.
This patch limits the schema down to four fields for Version2 by
default. It retains the old behavior of serializing all fields via:
llvm-profdata merge --memprof-version=2 --memprof-full-schema
This patch reduces the size of the indexed MemProf profile I have by
40% (1.6GB down to 1.0GB).
Commit: b9f2c16b50f68c978e90190f46a7c0db3f39e98c
https://github.com/llvm/llvm-project/commit/b9f2c16b50f68c978e90190f46a7c0db3f39e98c
Author: Fangrui Song <i at maskray.me>
Date: 2024-04-24 (Wed, 24 Apr 2024)
Changed paths:
M bolt/test/RISCV/unnamed-sym-no-entry.c
M lld/test/ELF/mips-eh_frame-pic.s
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/test/CodeGen/RISCV/fixups-diff.ll
M llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
R llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s
A llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s
M llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s
M llvm/test/MC/ELF/RISCV/gen-dwarf.s
M llvm/test/MC/RISCV/cfi-advance.s
M llvm/test/MC/RISCV/fde-reloc.s
M llvm/test/MC/RISCV/scoped-relaxation.s
Log Message:
-----------
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
Temporary symbols generated for .eh_frame and .debug_line have an empty
name, which appear in .symtab in the presence of RISC-V style linker
relaxation and will not be discarded by ld/objcopy --discard-locals
(-X).
In contrast, GNU assembler's riscv port assigns a fake name ".L0 " (with
a trailing space) to these symbols so that will be discarded by
ld/objcopy --discard-locals.
This patch matches the GNU behavior. Since Clang's RISC-V targets pass
-X to ld, and GNU ld defaults to -X for RISC-V targets, these ".L0 "
symbols will be discarded after linking by default, as expected by
users.
The llvm-symbolizer special case for RISC-V `SF_FormatSpecific` symbols
https://reviews.llvm.org/D98669 needs to be adjusted.
Note: `"":` in assembly currently crashes.
Commit: 8ba2a335416f0c692dde877a3b2d8acdde522c9c
https://github.com/llvm/llvm-project/commit/8ba2a335416f0c692dde877a3b2d8acdde522c9c
Author: Andrew Gozillon <Andrew.Gozillon at amd.com>
Date: 2024-05-01 (Wed, 01 May 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/RISCV/unnamed-sym-no-entry.c
A bolt/test/X86/indirect-goto-pie.test
M bolt/test/X86/shrinkwrapping-do-not-pessimize.s
R bolt/test/runtime/X86/Inputs/indirect_goto.c
R bolt/test/runtime/X86/indirect-goto-pie.test
M clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp
M clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt
A clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp
A clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.h
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/docs/clang-tidy/checks/bugprone/return-const-ref-from-parameter.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string.h
M clang-tools-extra/test/clang-tidy/checkers/abseil/redundant-strcat-calls.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp
M clang/cmake/caches/Release.cmake
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/ExtractAPI/API.h
M clang/include/clang/ExtractAPI/APIRecords.inc
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/include/clang/ExtractAPI/ExtractAPIVisitor.h
M clang/include/clang/Lex/HeaderSearch.h
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/WebAssembly.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/ExtractAPI/API.cpp
M clang/lib/ExtractAPI/DeclarationFragments.cpp
M clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaRISCVVectorLookup.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vreinterpret.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_ext_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_trunc_v.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vreinterpret.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlse16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg8e16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg4ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
M clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
M clang/test/CodeGen/builtins-wasm.c
M clang/test/CodeGen/ms-intrinsics-other.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGenOpenCL/builtins-generic-amdgcn.cl
M clang/test/Driver/amdgpu-toolchain.c
M clang/test/Driver/fast-math.c
M clang/test/ExtractAPI/anonymous_record_no_typedef.c
M clang/test/ExtractAPI/enum.c
M clang/test/ExtractAPI/function_noexcepts.cpp
M clang/test/ExtractAPI/methods.cpp
M clang/test/ExtractAPI/objc_block.m
M clang/test/ExtractAPI/typedef_anonymous_record.c
M clang/test/ExtractAPI/typedef_struct_enum.c
M clang/test/Headers/wasm.c
A clang/test/Modules/prune-non-affecting-module-map-files-textual.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/wasm-target-features.c
M clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
M clang/test/Sema/aarch64-sme-func-attrs.c
R clang/test/SemaCXX/PR41441.cpp
M clang/test/SemaCXX/template-specialization.cpp
M clang/tools/c-index-test/c-index-test.c
M clang/tools/driver/cc1_main.cpp
M clang/tools/libclang/CXSourceLocation.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/libclang/LibclangTest.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M compiler-rt/lib/fuzzer/build.sh
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/ctx_profile/CMakeLists.txt
A compiler-rt/test/ctx_profile/Unit/lit.site.cfg.py.in
M compiler-rt/test/memprof/CMakeLists.txt
A compiler-rt/test/memprof/Unit/lit.site.cfg.py.in
M flang/docs/Preprocessing.md
M flang/include/flang/Lower/Allocatable.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/preprocessor.h
M flang/include/flang/Runtime/numeric.h
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/type.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/HostAssociations.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/ReductionProcessor.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp
M flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp
M flang/lib/Parser/Fortran-parsers.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/program-tree.cpp
M flang/lib/Semantics/program-tree.h
M flang/lib/Semantics/resolve-names.cpp
M flang/runtime/edit-output.cpp
M flang/runtime/numeric.cpp
M flang/test/Driver/bbc-mlir-pass-pipeline.f90
R flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
M flang/test/Driver/mlir-debug-pass-pipeline.f90
M flang/test/Driver/mlir-pass-pipeline.f90
M flang/test/Fir/array-value-copy-2.fir
M flang/test/Fir/basic-program.fir
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Fir/loop01.fir
M flang/test/Fir/loop02.fir
M flang/test/Lower/CUDA/cuda-allocatable.cuf
M flang/test/Lower/HLFIR/internal-procedures.f90
A flang/test/Lower/Intrinsics/shape.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenMP/FIR/copyin.f90
M flang/test/Lower/OpenMP/FIR/flush.f90
M flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90
M flang/test/Lower/OpenMP/FIR/location.f90
M flang/test/Lower/OpenMP/FIR/master.f90
M flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90
M flang/test/Lower/OpenMP/FIR/parallel-sections.f90
M flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90
M flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90
M flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/FIR/target.f90
M flang/test/Lower/OpenMP/FIR/unstructured.f90
M flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90
M flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90
M flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90
M flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90
M flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/FIR/wsloop-simd.f90
M flang/test/Lower/OpenMP/FIR/wsloop-variable.f90
M flang/test/Lower/OpenMP/FIR/wsloop.f90
M flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90
M flang/test/Lower/OpenMP/copyin.f90
M flang/test/Lower/OpenMP/default-clause-byref.f90
M flang/test/Lower/OpenMP/default-clause.f90
A flang/test/Lower/OpenMP/function-filtering-3.f90
M flang/test/Lower/OpenMP/hlfir-wsloop.f90
M flang/test/Lower/OpenMP/lastprivate-commonblock.f90
M flang/test/Lower/OpenMP/lastprivate-iv.f90
M flang/test/Lower/OpenMP/location.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
M flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
M flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90
A flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90
M flang/test/Lower/OpenMP/parallel-reduction-array.f90
M flang/test/Lower/OpenMP/parallel-reduction-array2.f90
M flang/test/Lower/OpenMP/parallel-reduction3.f90
M flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90
M flang/test/Lower/OpenMP/parallel-wsloop.f90
M flang/test/Lower/OpenMP/stop-stmt-in-region.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/unstructured.f90
M flang/test/Lower/OpenMP/wsloop-chunks.f90
M flang/test/Lower/OpenMP/wsloop-collapse.f90
M flang/test/Lower/OpenMP/wsloop-monotonic.f90
M flang/test/Lower/OpenMP/wsloop-nonmonotonic.f90
M flang/test/Lower/OpenMP/wsloop-ordered.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-add.f90
M flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array.f90
M flang/test/Lower/OpenMP/wsloop-reduction-array2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-iand.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-ior.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90
M flang/test/Lower/OpenMP/wsloop-reduction-max.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min.f90
M flang/test/Lower/OpenMP/wsloop-reduction-min2.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90
M flang/test/Lower/OpenMP/wsloop-reduction-mul.f90
M flang/test/Lower/OpenMP/wsloop-reduction-multi.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M flang/test/Lower/OpenMP/wsloop-unstructured.f90
M flang/test/Lower/OpenMP/wsloop-variable.f90
M flang/test/Lower/OpenMP/wsloop.f90
M flang/test/Parser/unrecognized-dir.f90
A flang/test/Preprocessing/backslash-contin1.F90
A flang/test/Semantics/arg-convert.f90
M flang/test/Semantics/declarations03.f90
M flang/test/Transforms/omp-reduction-cfg-conversion.fir
M flang/unittests/Runtime/NumericalFormatTest.cpp
M flang/unittests/Runtime/RuntimeCrashTest.cpp
M libc/config/linux/syscall_numbers.h.inc
M libc/include/assert.h.def
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/assert-macros.h
M libc/src/sys/stat/linux/chmod.cpp
M libc/test/UnitTest/CMakeLists.txt
A libc/test/UnitTest/FEnvSafeTest.cpp
A libc/test/UnitTest/FEnvSafeTest.h
M libc/test/include/CMakeLists.txt
A libc/test/include/assert_test.cpp
M libc/test/src/fenv/CMakeLists.txt
M libc/test/src/fenv/enabled_exceptions_test.cpp
M libc/test/src/fenv/exception_flags_test.cpp
M libc/test/src/fenv/exception_status_test.cpp
A libc/test/src/fenv/excepts.h
M libc/test/src/fenv/feclearexcept_test.cpp
M libc/test/src/fenv/feenableexcept_test.cpp
M libc/test/src/fenv/feholdexcept_test.cpp
M libc/test/src/fenv/feupdateenv_test.cpp
M libc/test/src/fenv/getenv_and_setenv_test.cpp
M libc/test/src/fenv/rounding_mode_test.cpp
M libc/test/src/math/CeilTest.h
M libc/test/src/math/CopySignTest.h
M libc/test/src/math/FAbsTest.h
M libc/test/src/math/FDimTest.h
M libc/test/src/math/FMaxTest.h
M libc/test/src/math/FMinTest.h
M libc/test/src/math/FModTest.h
M libc/test/src/math/FloorTest.h
M libc/test/src/math/FmaTest.h
M libc/test/src/math/FrexpTest.h
M libc/test/src/math/HypotTest.h
M libc/test/src/math/ILogbTest.h
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/LogbTest.h
M libc/test/src/math/ModfTest.h
M libc/test/src/math/NextAfterTest.h
M libc/test/src/math/RIntTest.h
M libc/test/src/math/RemQuoTest.h
M libc/test/src/math/RoundEvenTest.h
M libc/test/src/math/RoundTest.h
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/SqrtTest.h
M libc/test/src/math/TruncTest.h
M libc/test/src/math/exhaustive/fmod_generic_impl_test.cpp
M libc/test/src/math/smoke/CanonicalizeTest.h
M libc/test/src/math/smoke/CeilTest.h
M libc/test/src/math/smoke/CopySignTest.h
M libc/test/src/math/smoke/FAbsTest.h
M libc/test/src/math/smoke/FDimTest.h
M libc/test/src/math/smoke/FMaxTest.h
M libc/test/src/math/smoke/FMaximumMagNumTest.h
M libc/test/src/math/smoke/FMaximumMagTest.h
M libc/test/src/math/smoke/FMaximumNumTest.h
M libc/test/src/math/smoke/FMaximumTest.h
M libc/test/src/math/smoke/FMinTest.h
M libc/test/src/math/smoke/FMinimumMagNumTest.h
M libc/test/src/math/smoke/FMinimumMagTest.h
M libc/test/src/math/smoke/FMinimumNumTest.h
M libc/test/src/math/smoke/FMinimumTest.h
M libc/test/src/math/smoke/FModTest.h
M libc/test/src/math/smoke/FloorTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/FrexpTest.h
M libc/test/src/math/smoke/FromfpTest.h
M libc/test/src/math/smoke/FromfpxTest.h
M libc/test/src/math/smoke/HypotTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/LogbTest.h
M libc/test/src/math/smoke/ModfTest.h
M libc/test/src/math/smoke/NextAfterTest.h
M libc/test/src/math/smoke/NextDownTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/NextUpTest.h
M libc/test/src/math/smoke/RIntTest.h
M libc/test/src/math/smoke/RemQuoTest.h
M libc/test/src/math/smoke/RoundEvenTest.h
M libc/test/src/math/smoke/RoundTest.h
M libc/test/src/math/smoke/RoundToIntegerTest.h
M libc/test/src/math/smoke/SqrtTest.h
M libc/test/src/math/smoke/TruncTest.h
M libc/test/src/math/smoke/UfromfpTest.h
M libc/test/src/math/smoke/UfromfpxTest.h
M libc/test/src/math/smoke/nan_test.cpp
M libc/test/src/math/smoke/nanf128_test.cpp
M libc/test/src/math/smoke/nanf_test.cpp
M libc/test/src/math/smoke/nanl_test.cpp
M libclc/cmake/modules/AddLibclc.cmake
M libcxx/benchmarks/CMakeLists.txt
A libcxx/benchmarks/std_format_spec_string_unicode_escape.bench.cpp
M libcxx/include/__numeric/saturation_arithmetic.h
M libcxx/modules/std.compat/cstdlib.inc
M libcxx/src/time_zone.cpp
M libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp
M lld/ELF/Arch/RISCV.cpp
A lld/test/ELF/lto/i386-global-offset-table.ll
A lld/test/ELF/lto/x86-64-global-offset-table.ll
M lld/test/ELF/mips-eh_frame-pic.s
M lldb/CMakeLists.txt
M lldb/docs/conf.py
M lldb/docs/index.rst
R lldb/docs/lldb-gdb-remote.txt
A lldb/docs/resources/lldbgdbremote.md
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ThreadedCommunication.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Target/TargetList.h
M lldb/include/lldb/Target/Thread.h
M lldb/include/lldb/Utility/Broadcaster.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBCommunication.cpp
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBEvent.cpp
M lldb/source/API/SBProcess.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/API/SBThread.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ThreadedCommunication.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetList.cpp
M lldb/source/Target/Thread.cpp
M lldb/source/Utility/Broadcaster.cpp
M lldb/test/API/macosx/ctf/Makefile
M lldb/test/API/macosx/ctf/TestCTF.py
M lldb/test/API/macosx/ctf/test.c
M llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/LangRef.rst
A llvm/docs/MemoryModelRelaxationAnnotations.rst
M llvm/docs/Reference.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/Security.rst
M llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp
M llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineInstr.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h
M llvm/include/llvm/Frontend/OpenMP/OMP.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/InstrTypes.h
A llvm/include/llvm/IR/MemoryModelRelaxationAnnotations.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/ProfileData/InstrProfWriter.h
M llvm/include/llvm/ProfileData/MemProf.h
R llvm/include/llvm/Support/RISCVISAInfo.h
A llvm/include/llvm/Support/RISCVISAUtils.h
M llvm/include/llvm/TargetParser/CMakeLists.txt
A llvm/include/llvm/TargetParser/RISCVISAInfo.h
M llvm/include/llvm/Transforms/Utils/Local.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CalcSpillWeights.cpp
M llvm/lib/CodeGen/CodeGenCommonISel.cpp
M llvm/lib/CodeGen/EarlyIfConversion.cpp
M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/InlineSpiller.cpp
M llvm/lib/CodeGen/LiveVariables.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineCSE.cpp
M llvm/lib/CodeGen/MachineCombiner.cpp
M llvm/lib/CodeGen/MachineCopyPropagation.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/ModuloSchedule.cpp
M llvm/lib/CodeGen/PHIElimination.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp
M llvm/lib/Frontend/OpenMP/OMP.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/CMakeLists.txt
M llvm/lib/IR/Instruction.cpp
A llvm/lib/IR/MemoryModelRelaxationAnnotations.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/ELFObjectWriter.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/ModuleSymbolTable.cpp
M llvm/lib/ProfileData/InstrProfWriter.cpp
M llvm/lib/ProfileData/MemProf.cpp
M llvm/lib/Support/CMakeLists.txt
R llvm/lib/Support/RISCVISAInfo.cpp
A llvm/lib/Support/RISCVISAUtils.cpp
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
M llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
M llvm/lib/Target/ARM/ARMSubtarget.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
M llvm/lib/Target/ARM/MVEVPTBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
M llvm/lib/Target/BPF/BPFTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
M llvm/lib/Target/M68k/M68kISelLowering.cpp
M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
M llvm/lib/Target/Mips/MipsExpandPseudo.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/RISCV.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86CmovConversion.cpp
M llvm/lib/Target/X86/X86FixupSetCC.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86FloatingPoint.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
M llvm/lib/Target/Xtensa/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp
A llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h
M llvm/lib/Target/Xtensa/Xtensa.td
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
M llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
A llvm/lib/Target/Xtensa/XtensaCallingConv.td
A llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
A llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
M llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
M llvm/lib/Target/Xtensa/XtensaFrameLowering.h
M llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
M llvm/lib/Target/Xtensa/XtensaISelLowering.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
M llvm/lib/Target/Xtensa/XtensaInstrInfo.h
M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
M llvm/lib/Target/Xtensa/XtensaOperands.td
A llvm/lib/Target/Xtensa/XtensaOperators.td
M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
A llvm/lib/Target/Xtensa/XtensaUtils.cpp
A llvm/lib/Target/Xtensa/XtensaUtils.h
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/TargetParser/RISCVTargetParser.cpp
M llvm/lib/Transforms/Coroutines/CoroInstr.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/ValueTracking/known-non-zero.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
A llvm/test/CodeGen/AArch64/concatbinop.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll
M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
A llvm/test/CodeGen/AMDGPU/mmra.ll
A llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/Mips/atomic-min-max.ll
M llvm/test/CodeGen/RISCV/O0-pipeline.ll
M llvm/test/CodeGen/RISCV/O3-pipeline.ll
M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
M llvm/test/CodeGen/RISCV/fixups-diff.ll
A llvm/test/CodeGen/RISCV/pr89833.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
A llvm/test/CodeGen/RISCV/rvv/commutable.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
M llvm/test/CodeGen/RISCV/xaluo.ll
A llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll
A llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll
A llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll
M llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll
A llvm/test/CodeGen/SPIRV/types/or-i1.ll
A llvm/test/CodeGen/Xtensa/call.ll
A llvm/test/CodeGen/Xtensa/calling-conv.ll
A llvm/test/CodeGen/Xtensa/constantpool.ll
A llvm/test/CodeGen/Xtensa/stack-access.ll
M llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
M llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
M llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
R llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s
A llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s
M llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s
M llvm/test/Instrumentation/HWAddressSanitizer/basic.ll
A llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll
M llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll
M llvm/test/LTO/X86/codemodel-2.ll
M llvm/test/LTO/X86/codemodel-3.ll
M llvm/test/LTO/X86/largedatathreshold-1.ll
M llvm/test/LTO/X86/largedatathreshold-2.ll
M llvm/test/LTO/X86/largedatathreshold-3.ll
M llvm/test/MC/ELF/RISCV/gen-dwarf.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/cfi-advance.s
M llvm/test/MC/RISCV/fde-reloc.s
M llvm/test/MC/RISCV/rv32dc-valid.s
M llvm/test/MC/RISCV/rv32fc-valid.s
M llvm/test/MC/RISCV/rv32zacas-invalid.s
M llvm/test/MC/RISCV/rv32zacas-valid.s
M llvm/test/MC/RISCV/rv64dc-valid.s
M llvm/test/MC/RISCV/rv64zacas-valid.s
M llvm/test/MC/RISCV/rvzabha-invalid.s
M llvm/test/MC/RISCV/rvzabha-valid.s
M llvm/test/MC/RISCV/rvzabha-zacas-valid.s
M llvm/test/MC/RISCV/scoped-relaxation.s
M llvm/test/MC/Xtensa/Core/invalid.s
A llvm/test/MC/Xtensa/directive-literal.s
A llvm/test/MC/Xtensa/invalid-literal.s
M llvm/test/TableGen/ContextlessPredicates.td
M llvm/test/TableGen/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
M llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
M llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-input-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
M llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
M llvm/test/TableGen/GlobalISelEmitter-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
M llvm/test/TableGen/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
M llvm/test/TableGen/GlobalISelEmitterFlags.td
M llvm/test/TableGen/GlobalISelEmitterHwModes.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
M llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
M llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
M llvm/test/TableGen/GlobalISelEmitterRegSequence.td
M llvm/test/TableGen/GlobalISelEmitterSubreg.td
M llvm/test/TableGen/GlobalISelEmitterVariadic.td
M llvm/test/TableGen/HasNoUse.td
M llvm/test/TableGen/address-space-patfrags.td
M llvm/test/TableGen/gisel-physreg-input.td
M llvm/test/TableGen/immarg-predicated.td
M llvm/test/TableGen/immarg.td
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
A llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll
M llvm/test/Transforms/GVN/condprop.ll
A llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll
M llvm/test/Transforms/InstCombine/add4.ll
M llvm/test/Transforms/InstCombine/bit_ceil.ll
M llvm/test/Transforms/InstCombine/bit_floor.ll
M llvm/test/Transforms/InstCombine/cmp-intrinsic.ll
M llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll
M llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll
M llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll
M llvm/test/Transforms/InstCombine/ctpop-cttz.ll
M llvm/test/Transforms/InstCombine/ctpop-pow2.ll
M llvm/test/Transforms/InstCombine/ctpop.ll
M llvm/test/Transforms/InstCombine/cttz-abs.ll
M llvm/test/Transforms/InstCombine/cttz-negative.ll
M llvm/test/Transforms/InstCombine/cttz.ll
M llvm/test/Transforms/InstCombine/ffs-1.ll
M llvm/test/Transforms/InstCombine/ffs-i16.ll
M llvm/test/Transforms/InstCombine/fls-i16.ll
M llvm/test/Transforms/InstCombine/fls.ll
M llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
M llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll
M llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll
M llvm/test/Transforms/InstCombine/freeze.ll
M llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll
M llvm/test/Transforms/InstCombine/intrinsic-select.ll
M llvm/test/Transforms/InstCombine/intrinsics.ll
M llvm/test/Transforms/InstCombine/ispow2.ll
M llvm/test/Transforms/InstCombine/known-non-zero.ll
M llvm/test/Transforms/InstCombine/known-phi-recurse.ll
M llvm/test/Transforms/InstCombine/loadstore-alignment.ll
M llvm/test/Transforms/InstCombine/memcpy-from-global.ll
M llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll
M llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll
M llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll
M llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/sext.ll
M llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
M llvm/test/Transforms/InstCombine/sub-xor.ll
M llvm/test/Transforms/InstCombine/xor.ll
M llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll
M llvm/test/Transforms/InstSimplify/ConstProp/gep-alias.ll
M llvm/test/Transforms/InstSimplify/past-the-end.ll
A llvm/test/Transforms/LoopUnroll/unroll-loads-cse.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll
M llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
M llvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll
A llvm/test/Transforms/SimplifyCFG/mmra.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
A llvm/test/Verifier/mmra-allowed.ll
A llvm/test/Verifier/mmra.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/llvm-profdata/memprof-merge-v0.test
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/Analysis/LoadsTest.cpp
M llvm/unittests/CodeGen/MachineInstrTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.cpp
M llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
M llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp
M llvm/unittests/Frontend/OpenMPCompositionTest.cpp
M llvm/unittests/IR/CMakeLists.txt
M llvm/unittests/IR/IntrinsicsTest.cpp
A llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp
M llvm/unittests/IR/PatternMatch.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/unittests/Support/CMakeLists.txt
R llvm/unittests/Support/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/CMakeLists.txt
A llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
A llvm/utils/TableGen/ARMTargetDefEmitter.cpp
M llvm/utils/TableGen/CMakeLists.txt
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
M mlir/CMakeLists.txt
M mlir/cmake/modules/AddMLIR.cmake
M mlir/cmake/modules/CMakeLists.txt
M mlir/cmake/modules/MLIRConfig.cmake.in
M mlir/docs/DefiningDialects/Operations.md
M mlir/docs/Tutorials/UnderstandingTheIRStructure.md
M mlir/include/mlir-c/Dialect/LLVM.h
M mlir/include/mlir-c/Dialect/SparseTensor.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SCF/Transforms/Passes.h
M mlir/include/mlir/Dialect/SCF/Transforms/Passes.td
M mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h
M mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
M mlir/include/mlir/TableGen/CodeGenHelpers.h
M mlir/include/mlir/Tools/lsp-server-support/Transport.h
M mlir/lib/Bindings/Python/DialectLLVM.cpp
M mlir/lib/Bindings/Python/DialectSparseTensor.cpp
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/CAPI/Dialect/SparseTensor.cpp
M mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SCF/Transforms/ForallToFor.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
M mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/TableGen/CodeGenHelpers.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Tools/lsp-server-support/Transport.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/python/mlir/dialects/LLVMOps.td
M mlir/python/mlir/dialects/llvm.py
M mlir/python/mlir/dialects/transform/interpreter/__init__.py
M mlir/test/CAPI/execution_engine.c
M mlir/test/CAPI/sparse_tensor.c
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
M mlir/test/Conversion/SCFToOpenMP/reductions.mlir
M mlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
M mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir
R mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/legalize-for-export.mlir
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Dialect/SCF/forall-to-for.mlir
A mlir/test/Dialect/SparseTensor/fuse_sparse_concat_with_extract_slice.mlir
M mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir
M mlir/test/Dialect/XeGPU/XeGPUOps.mlir
M mlir/test/Dialect/XeGPU/invalid.mlir
A mlir/test/Examples/NVGPU/Ch0.py
A mlir/test/Examples/NVGPU/Ch1.py
A mlir/test/Examples/NVGPU/Ch2.py
A mlir/test/Examples/NVGPU/Ch3.py
A mlir/test/Examples/NVGPU/Ch4.py
A mlir/test/Examples/NVGPU/Ch5.py
A mlir/test/Examples/NVGPU/lit.local.cfg
A mlir/test/Examples/NVGPU/tools/lit.local.cfg
A mlir/test/Examples/NVGPU/tools/nvdsl.py
A mlir/test/Examples/NVGPU/tools/nvgpucompiler.py
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
M mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir
M mlir/test/Target/LLVMIR/omptarget-wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-data-target-device.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-nested.mlir
M mlir/test/Target/LLVMIR/openmp-reduction.mlir
M mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir
M mlir/test/lib/Dialect/Test/CMakeLists.txt
M mlir/test/lib/Dialect/Test/TestDialect.cpp
M mlir/test/lib/Dialect/Test/TestOps.cpp
A mlir/test/mlir-tblgen/shard-op-defs.td
M mlir/test/python/dialects/llvm.py
M mlir/test/python/dialects/sparse_tensor/dialect.py
M mlir/test/python/dialects/transform_interpreter.py
A mlir/tools/mlir-src-sharder/CMakeLists.txt
A mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpGenHelpers.cpp
M mlir/tools/mlir-tblgen/OpGenHelpers.h
M mlir/unittests/CMakeLists.txt
A mlir/unittests/Tools/CMakeLists.txt
A mlir/unittests/Tools/lsp-server-support/CMakeLists.txt
A mlir/unittests/Tools/lsp-server-support/Transport.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl
A utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/tblgen.bzl
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/704a45d04a93...8ba2a335416f
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