[all-commits] [llvm/llvm-project] f565b7: [RISCV] Handle fixed length vectors with exact VLE...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f565b79f9fc278d37e884276212455920b51b47a
      https://github.com/llvm/llvm-project/commit/f565b79f9fc278d37e884276212455920b51b47a
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-05-01 (Wed, 01 May 2024)

  Changed paths:
    M llvm/include/llvm/Support/TypeSize.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll

  Log Message:
  -----------
  [RISCV] Handle fixed length vectors with exact VLEN in lowerINSERT_SUBVECTOR (#84107)

This is the insert_subvector equivalent to #79949, where we can avoid
sliding up by the full LMUL amount if we know the exact subregister the
subvector will be inserted into.

This mirrors the lowerEXTRACT_SUBVECTOR changes in that we handle this
in two parts:

- We handle fixed length subvector types by converting the subvector to
a scalable vector. But unlike EXTRACT_SUBVECTOR, we may also need to
convert the vector being inserted into too.

- Whenever we don't need a vslideup because either the subvector fits
exactly into a vector register group *or* the vector is undef, we need
to emit an insert_subreg ourselves because RISCVISelDAGToDAG::Select
doesn't correctly handle fixed length subvectors yet: see d7a28f7ad

A subvector exactly fits into a vector register group if its size is a
known multiple of the size of a vector register, and this adds a new
overload for TypeSize::isKnownMultipleOf for scalable to scalable
comparisons to help reason about this.

I've left RISCVISelDAGToDAG::Select untouched for now (minus relaxing an
invariant), so that the insert_subvector and extract_subvector code
paths are the same.

We should teach it to properly handle fixed length subvectors in a
follow-up patch, so that the "exact subregsiter" logic is handled in one
place instead of being spread across both RISCVISelDAGToDAG.cpp and
RISCVISelLowering.cpp.



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