[all-commits] [llvm/llvm-project] 940ef9: [RISCV] Remove hasSideEffects=1 for saturating/fau...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 940ef9687f5f19ce02b7fa5d2eb6225f458fbdd9
      https://github.com/llvm/llvm-project/commit/940ef9687f5f19ce02b7fa5d2eb6225f458fbdd9
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-30 (Tue, 30 Apr 2024)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/commutable.ll
    M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

  Log Message:
  -----------
  [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions

Marking them as `hasSideEffects=1` stops some optimizations.

According to `Target.td`:

> // Does the instruction have side effects that are not captured by any
> // operands of the instruction or other flags?
> bit hasSideEffects = ?;

It seems we don't need to set `hasSideEffects` for vleNff since we have
modelled `vl` as an output operand.

As for saturating instructions, I think that explicit Def/Use list
is kind of side effects captured by any operands of the instruction,
so we don't need to set `hasSideEffects` either. And I have just
investigated AArch64's implementation, they don't set this flag and
don't add `Def` list.

These changes make optimizations like `performCombineVMergeAndVOps`
and MachineCSE possible for these instructions.

As a consequence, `copyprop.mir` can't test what we want to test in
https://reviews.llvm.org/D155140, so we replace `vssra.vi` with a
VCIX instruction (it has side effects).

Reviewers: jacquesguan, topperc, preames, asb, lukel97

Reviewed By: topperc, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/90049



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