[all-commits] [llvm/llvm-project] 618adc: [RISCV] Support instruction sizes up to 176-bits i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 618adc762e95b33576c42be8912bb48dd0fdff94
      https://github.com/llvm/llvm-project/commit/618adc762e95b33576c42be8912bb48dd0fdff94
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-29 (Mon, 29 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    A llvm/test/MC/RISCV/large-instructions.s

  Log Message:
  -----------
  [RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)

We don't have any instructions defined yet, but that we can still read the correct number of bytes when disassembling. This should better match GNU objdump behavior.



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