[all-commits] [llvm/llvm-project] 80b815: [𝘀𝗽𝗿] initial version

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-remove-sew-operand-for-loadstore-and-sew-aware-pseudos
  Home:   https://github.com/llvm/llvm-project
  Commit: 80b815ef708b32a99a0b986f012b96eed9dd729c
      https://github.com/llvm/llvm-project/commit/80b815ef708b32a99a0b986f012b96eed9dd729c
  Author: wangpc <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-28 (Sun, 28 Apr 2024)

  Changed paths:
    M llvm/include/llvm/TargetParser/RISCVTargetParser.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/copyprop.mir
    M llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll
    M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
    M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
    M llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll
    M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
    M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.6-beta.1



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