[all-commits] [llvm/llvm-project] 73472c: [SelectionDAG] Treat CopyFromReg as freezing the v...

[Björn Pettersson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73472c5996716cda0dbb3ddb788304e0e7e6a323
      https://github.com/llvm/llvm-project/commit/73472c5996716cda0dbb3ddb788304e0e7e6a323
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/combine-mul.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/bfloat-convert.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
    M llvm/test/CodeGen/RISCV/iabs.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/abdu-vector-128.ll
    M llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
    M llvm/test/CodeGen/X86/avx512-broadcast-arith.ll
    M llvm/test/CodeGen/X86/combine-mul.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/X86/fold-masked-merge.ll
    M llvm/test/CodeGen/X86/freeze-binary.ll
    M llvm/test/CodeGen/X86/freeze-combine.ll
    M llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
    M llvm/test/CodeGen/X86/gfni-rotates.ll
    M llvm/test/CodeGen/X86/known-never-zero.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
    M llvm/test/CodeGen/X86/pr38539.ll
    M llvm/test/CodeGen/X86/pr62286.ll
    M llvm/test/CodeGen/X86/scheduler-backtracking.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
    M llvm/test/CodeGen/X86/vec_saddo.ll
    M llvm/test/CodeGen/X86/vec_ssubo.ll
    M llvm/test/CodeGen/X86/vec_uaddo.ll
    M llvm/test/CodeGen/X86/vec_usubo.ll
    M llvm/test/CodeGen/X86/vector-bo-select.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll

  Log Message:
  -----------
  [SelectionDAG] Treat CopyFromReg as freezing the value (#85932)

The description of CopyFromReg in ISDOpcodes.h says that the input
valus is defined outside the scope of the current SelectionDAG. I
think that means that we basically can treat it as a FREEZE in the
sense that it can be seen as neither being undef nor poison.

Being able to fold freeze(CopyFromReg) into CopyFromReg seems
useful to avoid regressions if we start to introduce freeze
instruction in DAGCombiner/foldBoolSelectToLogic, e.g. to solve
https://github.com/llvm/llvm-project/issues/84653

Things _not_ dealt with in this patch:
- Depending on calling convention an input argument can be passed
  also on the stack and not in a register. If it is allowed to treat
  an argument received in a register as not being poison, then I think
  we want to treat arguments received on the stack the same way. But
  then we need to attribute load instructions, or add explicit FREEZE
  when lowering formal arguments.
- A common pattern is that there is an AssertZext or AssertSext just
  after CopyFromReg. I think that if we treat CopyFromReg as never
  being poison, then it should be allowed to fold
     (freeze(AssertZext(CopyFromReg))) -> AssertZext(CopyFromReg))


  Commit: 8e2f6495c0bac1dd6ee32b6a0d24152c9c343624
      https://github.com/llvm/llvm-project/commit/8e2f6495c0bac1dd6ee32b6a0d24152c9c343624
  Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/freeze-binary.ll

  Log Message:
  -----------
  [DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)

Avoid turning a BUILD_VECTOR that can be recognized as "all zeros",
"all ones" or "constant" into something that depends on
freeze(undef), as that would destroy those properties.

Instead we replace undef by 0/-1 in such vectors, making it possible
to fold away the freeze. We typically use -1 if the BUILD_VECTOR
would identify as "all ones", and otherwise we use the value 0.


Compare: https://github.com/llvm/llvm-project/compare/431be8626696...8e2f6495c0ba

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