[all-commits] [llvm/llvm-project] c5f08b: [𝘀𝗽𝗿] changes introduced through rebase

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-add-generic-cpus-for-profiles
  Home:   https://github.com/llvm/llvm-project
  Commit: c5f08b61d9256807e3ac69828afe4cb07d3284e2
      https://github.com/llvm/llvm-project/commit/c5f08b61d9256807e3ac69828afe4cb07d3284e2
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
    M llvm/test/TableGen/riscv-target-def.td
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]


  Commit: 0fdb15089b326556e68e84558178a203e1d91dc7
      https://github.com/llvm/llvm-project/commit/0fdb15089b326556e68e84558178a203e1d91dc7
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
    M llvm/test/TableGen/riscv-target-def.td
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  Rebase

Created using spr 1.3.6-beta.1


Compare: https://github.com/llvm/llvm-project/compare/e03f2cdcc4d9...0fdb15089b32

To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications