[all-commits] [llvm/llvm-project] 7840fa: [RISCV] Fix doPRE not checking for ignored AVLs

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7840fa91a24ec7b9b771fd105ee1a9e1ba58837f
      https://github.com/llvm/llvm-project/commit/7840fa91a24ec7b9b771fd105ee1a9e1ba58837f
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-04-26 (Fri, 26 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Fix doPRE not checking for ignored AVLs

This fixes a crash introduced in 011a65353b8b4dc018541f86356f2dfa0f124f1a
that showed up when compiling with -mrvv-vector-bits=zvl. Beforehand, if a
basic block only contained vmv.s.x the AVL register in VSETVLIInfo would
have been NoRegister since it ignores VL.

In doPRE if AvailableInfo had a register AVL we checked that it dominated,
but coincidentally this failed for NoRegister. Now that the ignored AVL
case is separated out, check for it and bail.

As a side note, it turns out 011a65353b8b4dc018541f86356f2dfa0f124f1a is
less NFC than it seems as we can now do PRE on blocks where AvailableInfo's
AVL is VLMAX.



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