[all-commits] [llvm/llvm-project] 2c9e2e: [RISCV][ISel] Eliminate `andi rd, rs1, -1` instruc...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c9e2e9f0b75d6b023a388564092cc852ba29bd5
      https://github.com/llvm/llvm-project/commit/2c9e2e9f0b75d6b023a388564092cc852ba29bd5
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-04-25 (Thu, 25 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll

  Log Message:
  -----------
  [RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions (#89976)

Inspired by https://github.com/llvm/llvm-project/pull/89966, this patch
handles the special case `binop_allwusers<and> GPR:$rs1, 0xffffffff ->
copy $rs1` to avoid creating redundant `andi rd, rs1, -1` instructions.



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