[all-commits] [llvm/llvm-project] a35d7d: [AArch64][SelectionDAG] Correct the shift amounts ...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a35d7d7d124172632a9a108f76deba647f4da863
      https://github.com/llvm/llvm-project/commit/a35d7d7d124172632a9a108f76deba647f4da863
  Author: zhongyunde 00443407 <zhongyunde at huawei.com>
  Date:   2024-04-25 (Thu, 25 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/mul_pow2.ll

  Log Message:
  -----------
  [AArch64][SelectionDAG] Correct the shift amounts bound

Accord D152827, when the shift amounts is 4 or less, they are
cheap as a move.


  Commit: a6bdd6df23613c3ee5b3d7c31b1cf1fb78403a15
      https://github.com/llvm/llvm-project/commit/a6bdd6df23613c3ee5b3d7c31b1cf1fb78403a15
  Author: zhongyunde 00443407 <zhongyunde at huawei.com>
  Date:   2024-04-25 (Thu, 25 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/mul_pow2.ll

  Log Message:
  -----------
  [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add

Change the costmodel to lower a = b * C where C = (1 + 2^m) * 2^n + 1 to
          add   w8, w0, w0, lsl #m
          add   w0, w0, w8, lsl #n
Note: The latency of add can vary depending on the shirt amount
      They are cheap as a move when the shift amounts is 4 or less.
Fix part of https://github.com/llvm/llvm-project/issues/89430


Compare: https://github.com/llvm/llvm-project/compare/d5308949cf88...a6bdd6df2361

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