[all-commits] [llvm/llvm-project] f6d431: [CodeGen] Make the parameter TRI required in some ...

[Xu Zhang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6d431f208c0fa48827eac40e7acf788346a9967
      https://github.com/llvm/llvm-project/commit/f6d431f208c0fa48827eac40e7acf788346a9967
  Author: Xu Zhang <simonzgx at gmail.com>
  Date:   2024-04-24 (Wed, 24 Apr 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
    M llvm/lib/CodeGen/CalcSpillWeights.cpp
    M llvm/lib/CodeGen/CodeGenCommonISel.cpp
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/LiveVariables.cpp
    M llvm/lib/CodeGen/MachineCSE.cpp
    M llvm/lib/CodeGen/MachineCombiner.cpp
    M llvm/lib/CodeGen/MachineCopyPropagation.cpp
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
    M llvm/lib/CodeGen/MachineSink.cpp
    M llvm/lib/CodeGen/ModuloSchedule.cpp
    M llvm/lib/CodeGen/PHIElimination.cpp
    M llvm/lib/CodeGen/PeepholeOptimizer.cpp
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    M llvm/lib/CodeGen/StackSlotColoring.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
    M llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
    M llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
    M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/lib/Target/ARM/A15SDOptimizer.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
    M llvm/lib/Target/ARM/ARMFrameLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
    M llvm/lib/Target/ARM/MVEVPTBlockPass.cpp
    M llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
    M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
    M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/M68k/M68kISelLowering.cpp
    M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
    M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
    M llvm/lib/Target/X86/X86CmovConversion.cpp
    M llvm/lib/Target/X86/X86FixupSetCC.cpp
    M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
    M llvm/lib/Target/X86/X86FloatingPoint.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86MCInstLower.cpp
    M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

  Log Message:
  -----------
  [CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and  `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI  parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`,  `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.



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