[all-commits] [llvm/llvm-project] af81d8: [AArch64][CodeGen] Add patterns for small negative...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af81d8ec224900de7a4d2c96a675269499b55a0c
      https://github.com/llvm/llvm-project/commit/af81d8ec224900de7a4d2c96a675269499b55a0c
  Author: Allen <zhongyunde at huawei.com>
  Date:   2024-04-24 (Wed, 24 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/sve-vl-arith.ll
    M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

  Log Message:
  -----------
  [AArch64][CodeGen] Add patterns for small negative VScale const (#89607)

On AArch64, rdvl can accept a nagative value, while cntd/cntw/cnth can't.
As we do support VScale with a negative multiply value, so we did not limit
the negative value and instead took the hit of having the extra patterns according PR88108.
Also add NoUseScalarIncVL to avoid affecting patterns works for -mattr=+use-scalar-inc-vl
    
Fix https://github.com/llvm/llvm-project/issues/84620



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications