[all-commits] [llvm/llvm-project] 603ba4: [RISCV] Separate doLocalPostpass into new pass and...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 603ba4c59635ff5f8a54d1106719124aee20271d
      https://github.com/llvm/llvm-project/commit/603ba4c59635ff5f8a54d1106719124aee20271d
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-04-24 (Wed, 24 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)

This patch splits off part of the work to move vsetvli insertion to post
regalloc in #70549.

The doLocalPostpass operates outside of RISCVInsertVSETVLI's dataflow,
so we can move it to its own pass. We can then move it to post vector
regalloc which should be a smaller change.

A couple of things that are different from #70549:

- This manually fixes up the LiveIntervals rather than recomputing it
via createAndComputeVirtRegInterval. I'm not sure if there's much of a
difference with either.
- For the postpass it's sufficient enough to just check isUndef() in
hasUndefinedMergeOp, i.e. we don't need to lookup the def in VNInfo.

Running on llvm-test-suite and SPEC CPU 2017 there aren't any changes in
the number of vsetvlis removed. There are some minor scheduling diffs as
well as extra spills and less spills in some cases (caused by transient
vsetvlis existing between RISCVInsertVSETVLI and RISCVCoalesceVSETVLI
when vec regalloc happens), but they are minor and should go away once
we finish moving the rest of RISCVInsertVSETVLI.

We could also potentially turn off this pass for unoptimised builds.



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