[all-commits] [llvm/llvm-project] 34caaf: [LLVM][CodeGen][AArch64] Simplify lowering for pre...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34caafe84ffd8588e717c92da358ad9368cc4fe5
      https://github.com/llvm/llvm-project/commit/34caafe84ffd8588e717c92da358ad9368cc4fe5
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2024-04-23 (Tue, 23 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  Log Message:
  -----------
  [LLVM][CodeGen][AArch64] Simplify lowering for predicate inserts. (#89072)

The original code has an invalid use of UZP1 because the result vector
type does not match its input vector types. Rather than insert extra nop
casts I figure it would be better to use CONCAT_VECTORS because that's
the operation we're performing.

NOTE: This is a step to enable more asserts in verifyTargetSDNode.



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