[all-commits] [llvm/llvm-project] b64e48: [RISCV][TableGen] Generate RISCVTargetParserDef.in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b64e483785bfef5ec4977988543ed5cfaf62f306
      https://github.com/llvm/llvm-project/commit/b64e483785bfef5ec4977988543ed5cfaf62f306
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-22 (Mon, 22 Apr 2024)

  Changed paths:
    A llvm/test/TableGen/riscv-target-def.td
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  [RISCV][TableGen] Generate RISCVTargetParserDef.inc from the new RISCVExtension tblgen information. (#89335)

Instead of using RISCVISAInfo's extension information, use the extension
found in tblgen after #89326.
    
We still need to use RISCVISAInfo code to get the sorting rules for the
ISA string.
    
The ISA string we generate now is not quite the same extension we had
before. No implied extensions are included in the generate string unless
they are explicitly listed in RISCVProcessors.td. This primarily affects
Zicsr being implied by F, V implying Zve*, and Zvl*b implying a smaller
Zvl*b. All of these implication should be picked up when the string is
used by the frontend.
    
The benefit is that we get a more manageable ISA string for humans to
deal with.
    
This is a step towards generating RISCVISAInfo's extension list from
tblgen.



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