[all-commits] [llvm/llvm-project] cd0c94: [RISCV] Remove IsEABI from RISCVZC::getStackAdjBas...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cd0c94bb8558b6e26313694da18006a840521903
      https://github.com/llvm/llvm-project/commit/cd0c94bb8558b6e26313694da18006a840521903
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-18 (Thu, 18 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    A llvm/test/MC/RISCV/rv64e-zcmp-valid.s

  Log Message:
  -----------
  [RISCV] Remove IsEABI from RISCVZC::getStackAdjBase. (#89177)

The usage of IsEABI was only valid for RV32E. For RV64E, the stack
adjust
base needs to be 32 when ra,s0-s1 are being saved. Since it takes more
than 16 bytes to save 3 64-bit registers.
    
The spec lists the rv32e behavior explicitly, but not rv64e. My
assumption is that the only thing that changes with rv64e is which
registers can be used in the register list, but not how the register
list affects the stack_adj_base.



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