[all-commits] [llvm/llvm-project] ac39fa: [MLIR][Mem2Reg][LLVM] Enhance partial load support...

[Christian Ulmann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac39fa740b067f6197dca1caecc97c0da91ebf3d
      https://github.com/llvm/llvm-project/commit/ac39fa740b067f6197dca1caecc97c0da91ebf3d
  Author: Christian Ulmann <christianulmann at gmail.com>
  Date:   2024-04-18 (Thu, 18 Apr 2024)

  Changed paths:
    M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
    M mlir/lib/Transforms/Mem2Reg.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [MLIR][Mem2Reg][LLVM] Enhance partial load support (#89094)

This commit improves LLVM dialect's Mem2Reg interfaces to support
promotions of partial loads from larger memory slots. To support this,
the Mem2Reg interface methods are extended with additional data layout
parameters. The data layout is required to determine type sizes to
produce correct conversion sequences.

Note: There will be additional followups that introduce a similar
functionality for stores, and there are plans to support accesses into
the middle of memory slots.



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