[all-commits] [llvm/llvm-project] 3e64f8: [AArch64][CodeGen] Fix illegal register aliasing b...

[Nashe Mncube via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e64f8a4e74cdcaf5920879c86e7e0a827f6ec13
      https://github.com/llvm/llvm-project/commit/3e64f8a4e74cdcaf5920879c86e7e0a827f6ec13
  Author: Nashe Mncube <nashe.mncube at arm.com>
  Date:   2024-04-18 (Thu, 18 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/mops-register-alias.ll
    A llvm/test/MC/AArch64/armv9.3a-mops-register-aliasing.s

  Log Message:
  -----------
  [AArch64][CodeGen] Fix illegal register aliasing bug for mops instrs (#88869)

A bug was found where mops instructions were being generated that
aliased the source and size registers. This is unpredictable behaviour.
This patch uses the earlyclobber constraint on the input source
register so that it doesn't alias with the size register. Also a test is
introduced which checks affected instructions can't violate this
constraint.



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