[all-commits] [llvm/llvm-project] 471488: [mlir][python] Add `walk` method to PyOperationBas...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Wed Apr 17 17:18:21 PDT 2024
Branch: refs/heads/users/MaskRay/spr/utils-add-script-to-generate-elaborated-assembly-tests
Home: https://github.com/llvm/llvm-project
Commit: 47148832d4e3bf4901430732f1af6673147accb2
https://github.com/llvm/llvm-project/commit/47148832d4e3bf4901430732f1af6673147accb2
Author: Hideto Ueno <uenoku.tokotoko at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/PybindAdaptors.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/CAPI/ir.c
M mlir/test/python/ir/operation.py
Log Message:
-----------
[mlir][python] Add `walk` method to PyOperationBase (#87962)
This commit adds `walk` method to PyOperationBase that uses a python
object as a callback, e.g. `op.walk(callback)`. Currently callback must
return a walk result explicitly.
We(SiFive) have implemented walk method with python in our internal
python tool for a while. However the overhead of python is expensive and
it didn't scale well for large MLIR files. Just replacing walk with this
version reduced the entire execution time of the tool by 30~40% and
there are a few configs that the tool takes several hours to finish so
this commit significantly improves tool performance.
Commit: 1bccbe1f49abc39b9f980cf3f1b171da5541d1a4
https://github.com/llvm/llvm-project/commit/1bccbe1f49abc39b9f980cf3f1b171da5541d1a4
Author: martinboehme <mboehme at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Treat `BuiltinBitCastExpr` correctly in `PropagateResultObject()`. (#88875)
This patch includes a test that assert-fails without the fix.
Commit: 64c649585ca23a0c996d8814d2796cd348441d69
https://github.com/llvm/llvm-project/commit/64c649585ca23a0c996d8814d2796cd348441d69
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseObjc.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaDecl.cpp
Log Message:
-----------
[clang][NFC] Move `Sema::SkipBodyInfo` into namespace scope
This makes it forward-declarable, and needed from splitting `Sema` up.
Commit: 16f188761da1df6ba5e6627b8742aacfec8e9ec5
https://github.com/llvm/llvm-project/commit/16f188761da1df6ba5e6627b8742aacfec8e9ec5
Author: YunQiang Su <syq at debian.org>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
Log Message:
-----------
CompilerRT: Normalize COMPILER_RT_DEFAULT_TARGET_TRIPLE (#88835)
If LLVM is configured with -DLLVM_DEFAULT_TARGET_TRIPLE, or compiler_rt
is configured with -DCOMPILER_RT_DEFAULT_TARGET_TRIPLE, while the
argument is not normalized, such as Debian-style vendor-less triple,
clang will try to find libclang_rt in lib/<normalized_triple>, while
libclang_rt is placed into lib/<triple_arg>.
Let's also place libclang_rt into lib/<normalized_triple>.
Commit: b090569685699abe4a8031ad442a0f81e373146b
https://github.com/llvm/llvm-project/commit/b090569685699abe4a8031ad442a0f81e373146b
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Support Zama16b1p0 (#88474)
This patch adds the support for Zama16b version 1.0, which has been
added to RVA23U64 optional extensions recently
Commit: d35a64363bb851045387717d2ef7d6449b7b547f
https://github.com/llvm/llvm-project/commit/d35a64363bb851045387717d2ef7d6449b7b547f
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/test/SemaCXX/PR41441.cpp
Log Message:
-----------
Revert "Fix test from #83124 and #88902"
This reverts commit 0a789ea8a829da345e46d8224d73b2ddaba6969f.
Breaks builds, see discussion in https://github.com/llvm/llvm-project/pull/83124
Commit: dbda478693104f78b142375862d66f3369ad8c78
https://github.com/llvm/llvm-project/commit/dbda478693104f78b142375862d66f3369ad8c78
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
R clang/test/SemaCXX/PR41441.cpp
A clang/test/SemaCXX/instantiate-new-placement-size.cpp
Log Message:
-----------
Revert "[Clang][Sema] placement new initializes typedef array with correct size (#88902)"
This reverts commit 5c6af605b307213453a9a043532b9293db21b5c6.
Breaks builds, see discussion in https://github.com/llvm/llvm-project/pull/83124
Commit: dd84d23adc84cc0c3d2b8fb8f0c353279d99d27a
https://github.com/llvm/llvm-project/commit/dd84d23adc84cc0c3d2b8fb8f0c353279d99d27a
Author: Mikhail Goncharov <goncharov.mikhail at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/TreeTransform.h
R clang/test/SemaCXX/instantiate-new-placement-size.cpp
Log Message:
-----------
Revert "[Clang][Sema] placement new initializes typedef array with correct size (#83124)"
This reverts commit c309dc6d0759b23b570c563f611530ff1a49e1bd.
Breaks builds, see discussion in https://github.com/llvm/llvm-project/pull/83124
Commit: bc3620d3a8b1be9534a5635431b0aa09cc50ff3c
https://github.com/llvm/llvm-project/commit/bc3620d3a8b1be9534a5635431b0aa09cc50ff3c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-libcall-sincos-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-sincos.ll
M llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
Log Message:
-----------
AMDGPU: Move libcall simplify into PeepholeEP (#88853)
We were running this immediately on the incoming IR, which
is still littered with temporary allocas obscuring trivial values.
This needs to run after initial SROA to handle sincos insertion.
Commit: e11b17a4ed90e74147594012207fc35a60515944
https://github.com/llvm/llvm-project/commit/e11b17a4ed90e74147594012207fc35a60515944
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprObjC.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaPseudoObject.cpp
Log Message:
-----------
[clang][NFC] Refactor `Sema::CheckedConversionKind`
Convert it to scoped enum, and move it to namespace scope to enable forward declarations.
Commit: 49b209d0d1833a339e66735e1288c1805224603e
https://github.com/llvm/llvm-project/commit/49b209d0d1833a339e66735e1288c1805224603e
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
Log Message:
-----------
Revert "[Libomptarget] Rework Record & Replay to be a plugin member" (#89028)
Reverts llvm/llvm-project#88928
This broke the AMDGPU buildbots:
https://lab.llvm.org/buildbot/#/builders/193/builds/50201
https://lab.llvm.org/staging/#/builders/185/builds/5565
https://lab.llvm.org/buildbot/#/builders/259/builds/2955
Commit: 9f3334e9932fc9b55cd3590b140913222454c031
https://github.com/llvm/llvm-project/commit/9f3334e9932fc9b55cd3590b140913222454c031
Author: Matthias Springer <me at m-sp.org>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir
Log Message:
-----------
[mlir][SparseTensor] Add missing dependent dialect to pass (#88870)
This commit fixes the following error when stopping the sparse compiler
pipeline after bufferization (e.g., with `test-analysis-only`):
```
LLVM ERROR: Building op `vector.print` but it isn't known in this MLIRContext: the dialect may not be loaded or this operation hasn't been added by the dialect. See also https://mlir.llvm.org/getting_started/Faq/#registered-loaded-dependent-whats-up-with-dialects-management
```
Commit: 889dfd4ab35892840f2bd2d6d7fed6fac025e18e
https://github.com/llvm/llvm-project/commit/889dfd4ab35892840f2bd2d6d7fed6fac025e18e
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libc/src/__support/macros/sanitizer.h
Log Message:
-----------
[libc][msan] Fix "non-constexpr function '__msan_unpoison' cannot be used in a constant expression" (#88719)
Prior to this patch, calling `cpp::bit_cast<T>` in `constexpr`
expressions under `-fsanitize=memory` would fail with the following
message "non-constexpr function '__msan_unpoison' cannot be used in a
constant expression".
This patch makes sure that the `__msan_unpoison` expression is guarded
by `!__builtin_is_constant_evaluated()`.
Commit: 17b86d5978af8d171fa28763a9e5eba3ce93713a
https://github.com/llvm/llvm-project/commit/17b86d5978af8d171fa28763a9e5eba3ce93713a
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/CodeGen/X86/combine-ptest.ll
Log Message:
-----------
[X86][NFC] Add test cases for pr88958
Commit: d1a69e4a6ee0b04778da7728123c47eef2290564
https://github.com/llvm/llvm-project/commit/d1a69e4a6ee0b04778da7728123c47eef2290564
Author: shamithoke <152091883+shamithoke at users.noreply.github.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
Move gfni for bitreverse check out of SSSE3. (#88938)
For lowering bitreverse using GFNI, the check is put under SSSE3. This can be pulled out of SSSE3.
Co-authored-by: shami <shami_thoke at yahoo.com>
Commit: a16bb0701409376dee3a587ae351a6019d6de4e0
https://github.com/llvm/llvm-project/commit/a16bb0701409376dee3a587ae351a6019d6de4e0
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/dotest.py
Log Message:
-----------
[lldb][test] Improve invalid compiler error message
I was debugging space separation issues when passing user arguments
and noticed this error is really hard to read in that scenario.
Put "" around the invalid compiler name so you can tell whether
you have spaces around it that's causing the problem.
Commit: d9a5aa8e2d755643cf4e7fa86aa831ed226fe54d
https://github.com/llvm/llvm-project/commit/d9a5aa8e2d755643cf4e7fa86aa831ed226fe54d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
M llvm/test/Transforms/InstCombine/abs-1.ll
M llvm/test/Transforms/InstCombine/add-mask-neg.ll
M llvm/test/Transforms/InstCombine/add.ll
M llvm/test/Transforms/InstCombine/and-or-icmps.ll
M llvm/test/Transforms/InstCombine/and-xor-or.ll
M llvm/test/Transforms/InstCombine/and.ll
M llvm/test/Transforms/InstCombine/and2.ll
M llvm/test/Transforms/InstCombine/ashr-lshr.ll
M llvm/test/Transforms/InstCombine/ashr-or-mul-abs.ll
M llvm/test/Transforms/InstCombine/binop-and-shifts.ll
M llvm/test/Transforms/InstCombine/binop-of-displaced-shifts.ll
M llvm/test/Transforms/InstCombine/canonicalize-clamp-like-pattern-between-zero-and-positive-threshold.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sge-to-icmp-sle.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sgt-to-icmp-sgt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-sle-to-icmp-sle.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-slt-to-icmp-sgt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-uge-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ugt-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ule-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-constant-low-bit-mask-and-icmp-ult-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll
M llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll
M llvm/test/Transforms/InstCombine/cast-int-icmp-eq-0.ll
M llvm/test/Transforms/InstCombine/cast-unsigned-icmp-eqcmp-0.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/ctpop-cttz.ll
M llvm/test/Transforms/InstCombine/ctpop.ll
M llvm/test/Transforms/InstCombine/fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/fast-math.ll
M llvm/test/Transforms/InstCombine/fcmp-special.ll
M llvm/test/Transforms/InstCombine/fcmp.ll
M llvm/test/Transforms/InstCombine/fdiv.ll
M llvm/test/Transforms/InstCombine/fma.ll
M llvm/test/Transforms/InstCombine/fmul.ll
M llvm/test/Transforms/InstCombine/fneg-as-int.ll
M llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
M llvm/test/Transforms/InstCombine/fneg.ll
M llvm/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll
M llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll
M llvm/test/Transforms/InstCombine/fpcast.ll
M llvm/test/Transforms/InstCombine/fsub.ll
M llvm/test/Transforms/InstCombine/funnel.ll
M llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll
M llvm/test/Transforms/InstCombine/hoist-negation-out-of-bias-calculation.ll
M llvm/test/Transforms/InstCombine/hoist-not-from-ashr-operand.ll
M llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp.ll
M llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
M llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-vector.ll
M llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/masked-merge-add.ll
M llvm/test/Transforms/InstCombine/masked-merge-or.ll
M llvm/test/Transforms/InstCombine/masked-merge-xor.ll
M llvm/test/Transforms/InstCombine/min-positive.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/InstCombine/not-add.ll
M llvm/test/Transforms/InstCombine/not.ll
M llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
M llvm/test/Transforms/InstCombine/operand-complexity.ll
M llvm/test/Transforms/InstCombine/or.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll
M llvm/test/Transforms/InstCombine/pr53357.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-b.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-c.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-d.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
M llvm/test/Transforms/InstCombine/reuse-constant-from-select-in-icmp.ll
M llvm/test/Transforms/InstCombine/rotate.ll
M llvm/test/Transforms/InstCombine/saturating-add-sub.ll
M llvm/test/Transforms/InstCombine/select-of-bittest.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/select_meta.ll
M llvm/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll
M llvm/test/Transforms/InstCombine/sext.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-lshr.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation.ll
M llvm/test/Transforms/InstCombine/shift-logic.ll
M llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/signmask-of-sext-vs-of-shl-of-zext.ll
M llvm/test/Transforms/InstCombine/sub-not.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
M llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll
M llvm/test/Transforms/InstCombine/trunc.ll
M llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
M llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
M llvm/test/Transforms/InstCombine/variable-signext-of-variable-high-bit-extraction.ll
M llvm/test/Transforms/InstCombine/vec_sext.ll
M llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vector-casts.ll
M llvm/test/Transforms/InstCombine/vector-urem.ll
M llvm/test/Transforms/InstCombine/vector-xor.ll
M llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
M llvm/test/Transforms/InstSimplify/AndOrXor.ll
M llvm/test/Transforms/InstSimplify/call.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/constantfold-add-nuw-allones-to-allones.ll
M llvm/test/Transforms/InstSimplify/constantfold-shl-nuw-C-to-C.ll
M llvm/test/Transforms/InstSimplify/div.ll
M llvm/test/Transforms/InstSimplify/fast-math-strictfp.ll
M llvm/test/Transforms/InstSimplify/fast-math.ll
M llvm/test/Transforms/InstSimplify/fdiv.ll
M llvm/test/Transforms/InstSimplify/floating-point-arithmetic-strictfp.ll
M llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll
M llvm/test/Transforms/InstSimplify/floating-point-compare.ll
M llvm/test/Transforms/InstSimplify/fminmax-folds.ll
M llvm/test/Transforms/InstSimplify/fp-nan.ll
M llvm/test/Transforms/InstSimplify/icmp-bool-constant.ll
M llvm/test/Transforms/InstSimplify/icmp-not-bool-constant.ll
M llvm/test/Transforms/InstSimplify/ldexp.ll
M llvm/test/Transforms/InstSimplify/mul.ll
M llvm/test/Transforms/InstSimplify/negate.ll
M llvm/test/Transforms/InstSimplify/or.ll
M llvm/test/Transforms/InstSimplify/ptrmask.ll
M llvm/test/Transforms/InstSimplify/rem.ll
M llvm/test/Transforms/InstSimplify/saturating-add-sub.ll
M llvm/test/Transforms/InstSimplify/sdiv.ll
M llvm/test/Transforms/InstSimplify/select-inseltpoison.ll
M llvm/test/Transforms/InstSimplify/select.ll
M llvm/test/Transforms/InstSimplify/shift.ll
M llvm/test/Transforms/InstSimplify/srem.ll
M llvm/test/Transforms/InstSimplify/sub.ll
M llvm/test/Transforms/InstSimplify/xor.ll
M llvm/test/Transforms/Reassociate/inverses.ll
M llvm/test/Transforms/Reassociate/negation.ll
M llvm/unittests/IR/ConstantsTest.cpp
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch] Do not accept undef elements in m_AllOnes() and friends (#88217)
Change all the cstval_pred_ty based PatternMatch helpers (things like
m_AllOnes and m_Zero) to only allow poison elements inside vector
splats, not undef elements.
Historically, we used to represent non-demanded elements in vectors
using undef. Nowadays, we use poison instead. As such, I believe that
support for undef in vector splats is no longer useful.
At the same time, while poison splat elements are pretty much always
safe to ignore, this is not generally the case for undef elements. We
have existing miscompiles in our tests due to this (see the
masked-merge-*.ll tests changed here) and it's easy to miss such cases
in the future, now that we write tests using poison instead of undef
elements.
I think overall, keeping support for undef elements no longer makes
sense, and we should drop it. Once this is done consistently, I think we
may also consider allowing poison in m_APInt by default, as doing that
change is much less risky than doing the same with undef.
This change involves a substantial amount of test changes. For most
tests, I've just replaced undef with poison, as I don't think there is
value in retaining both. For some tests (where the distinction between
undef and poison is important), I've duplicated tests.
Commit: 971237dab259bdaa619403fc6472bd1758d4dc18
https://github.com/llvm/llvm-project/commit/971237dab259bdaa619403fc6472bd1758d4dc18
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/include/flang/Lower/CallInterface.h
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
A flang/test/Lower/HLFIR/internal-procedures-bindc-host.f90
M flang/test/Lower/HLFIR/internal-procedures.f90
M flang/test/Lower/OpenACC/acc-routine04.f90
M flang/test/Lower/OpenMP/threadprivate-host-association-2.f90
M flang/test/Lower/OpenMP/threadprivate-host-association.f90
M flang/test/Lower/character-elemental.f90
M flang/test/Lower/equivalence-with-host-assoc.f90
M flang/test/Lower/explicit-interface-results-2.f90
M flang/test/Lower/host-associated-functions.f90
M flang/test/Lower/host-associated-globals.f90
M flang/test/Lower/host-associated.f90
M flang/test/Lower/polymorphic.f90
Log Message:
-----------
[flang] Retain internal and BIND(C) host procedure link in FIR (#87796)
Currently, it is not possible to find back which fun.func is the host
procedure of some internal procedure because the mangling of the
internal procedure does not contain info about the BIND(C) name of the
host.
This info may be useful to ensure dwarf DW_TAG_subprogram of internal
procedures are nested under DW_TAG_subprogram of host procedures for
instance.
Commit: b512df660ef136f8bbd0895bf862a827923a6714
https://github.com/llvm/llvm-project/commit/b512df660ef136f8bbd0895bf862a827923a6714
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
M llvm/test/CodeGen/SPIRV/instructions/select-phi.ll
A llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll
M llvm/test/CodeGen/SPIRV/instructions/select.ll
A llvm/test/CodeGen/SPIRV/select-builtin.ll
R llvm/test/CodeGen/SPIRV/select.ll
Log Message:
-----------
[SPIR-V] Improve Tablegen instruction selection and account for a pointer size of the target (#88725)
This PR resolves the issue that SPIR-V Backend uses the notion of a
pointer size of the target, most notably, in legalizer code, but
Tablegen instruction selection in SPIR-V Backend doesn't account for a
pointer size of the target. See
https://github.com/llvm/llvm-project/issues/88723 for a detailed
description. There are 3 test cases attached to the PR that reproduced
the issue, when dealing with spirv32-spirv64 differences, and are
working correctly now with this PR.
Commit: 42d801d4e42ff8c47c3a24d562774851e3a424f5
https://github.com/llvm/llvm-project/commit/42d801d4e42ff8c47c3a24d562774851e3a424f5
Author: Vyacheslav Levytskyy <vyacheslav.levytskyy at intel.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
A llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll
M llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll
Log Message:
-----------
[SPIR-V] Account for zext in a llvm intrinsic call (#88903)
This PR addresses an issue that may arise when an integer argument size
differs from a machine word size for the target in a call to llvm
intrinsic. The following example demonstrates the issue:
```
@__const.test.arr = private unnamed_addr addrspace(2) constant [3 x i32] [i32 1, i32 2, i32 3]
define spir_func void @test() {
entry:
%arr = alloca [3 x i32], align 4
%dest = bitcast ptr %arr to ptr
call void @llvm.memcpy.p0.p2.i32(ptr align 4 %dest, ptr addrspace(2) align 4 @__const.test.arr, i32 1024, i1 false)
ret void
}
declare void @llvm.memcpy.p0.p2.i32(ptr nocapture writeonly, ptr addrspace(2) nocapture readonly, i32, i1)
```
Depending on the target this code may work or may fail without this PR
due to the fact that IR Translation step introduces additional `zext`
when type of the 3rd argument of `@llvm.memcpy.p0.p2.i32` differs from
machine word.
This PR addresses the issue by adding type deduction for a newly
inserted G_ZEXT generic opcode.
Commit: fa61f062a515be92a98cac64a9193498918c1225
https://github.com/llvm/llvm-project/commit/fa61f062a515be92a98cac64a9193498918c1225
Author: harishch4 <harishcse44 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Lower/OpenMP/threadprivate-hlfir.f90
A flang/test/Semantics/OpenMP/threadprivate07.f90
Log Message:
-----------
Fix threadprivate variable scope inside BLOCK construct. (#88921)
When a local variable inside a BLOCK construct is used as threadprivate
variable, llvm-flang throws below error:
> error: The THREADPRIVATE directive and the common block or variable in
it must appear in the same declaration section of a scoping unit
Commit: cbe148b730a04fc95eda9a43903f0af487884a96
https://github.com/llvm/llvm-project/commit/cbe148b730a04fc95eda9a43903f0af487884a96
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV][NFC] Remove the declaration of function `fixReduction`. (#88491)
Commit: a9bafe91dd088c5fa6f074c14dd3a1af25f00457
https://github.com/llvm/llvm-project/commit/a9bafe91dd088c5fa6f074c14dd3a1af25f00457
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Split VPWidenMemoryInstructionRecipe (NFCI). (#87411)
This patch introduces a new VPWidenMemoryRecipe base class and distinct
sub-classes to model loads and stores.
This is a first step in an effort to simplify and modularize code
generation for widened loads and stores and enable adding further more
specialized memory recipes.
PR: https://github.com/llvm/llvm-project/pull/87411
Commit: f4737a2edd900df661750116821806bb45e4086a
https://github.com/llvm/llvm-project/commit/f4737a2edd900df661750116821806bb45e4086a
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/stable_ir_values_funcs.ll.expected
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
update_test_checks: keep names stable with generated functions (#87988)
Collect the original check lines in a manner that is independent of
where the check lines appear in the file. This is so that we keep
FileCheck variable names stable even when --include-generated-funcs is
used.
Reported-by: Ruiling Song <ruiling.song at amd.com>
Commit: 3eb0ba34b0a2a29c2f34ead2b84fdf9b62cb29c1
https://github.com/llvm/llvm-project/commit/3eb0ba34b0a2a29c2f34ead2b84fdf9b62cb29c1
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Lower/OpenMP/FIR/if-clause.f90
M flang/test/Lower/OpenMP/FIR/loop-combined.f90
M flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90
M flang/test/Lower/OpenMP/FIR/simd.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-combined.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
M flang/test/Lower/OpenMP/simd.f90
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
Log Message:
-----------
[MLIR][Flang][OpenMP] Make omp.simdloop into a loop wrapper (#87365)
This patch updates the definition of `omp.simdloop` to enforce the
restrictions of a wrapper operation. It has been renamed to `omp.simd`,
to better reflect the naming used in the spec. All uses of "simdloop" in
function names have been updated accordingly.
Some changes to Flang lowering and OpenMP to LLVM IR translation are
introduced to prevent the introduction of compilation/test failures. The
eventual long term solution might be different.
Commit: 16b0be613205a37519e2bfec1a904ceaa89636e7
https://github.com/llvm/llvm-project/commit/16b0be613205a37519e2bfec1a904ceaa89636e7
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
Log Message:
-----------
[MLIR][OpenMP] NFC: Remove LoopControl parsing/printing code (#88909)
This patch removes the LoopControl parsing/printing functions that are
no longer used after transitioning `omp.simdloop` and `omp.taskloop`
into loop wrapper operations.
Commit: a02019960b1a693320cd43b0ed6653d95877b94f
https://github.com/llvm/llvm-project/commit/a02019960b1a693320cd43b0ed6653d95877b94f
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vxrm.mir
Log Message:
-----------
[RISCV] Assert only valid AVLs in doLocalPostpass are X0 or virtual regs. NFC
In vxrm.mir we were running RISCVInsertVSETVLI on pseudos that already had
vsetvlis inserted and their AVLs set to $noreg. (This happened to work
since doLocalPostpass got rid of the extra vsetvli)
This removes the vsetvlis from the test and enforces that the only valid
AVLs we work with are either X0 or virtual registers (or $noreg before
emitVSETVLIs), since we don't handle physical registers properly in
doLocalPostpass.
Commit: a634f3ef39c0c547b87f1ee4ebe02ee3a256587f
https://github.com/llvm/llvm-project/commit/a634f3ef39c0c547b87f1ee4ebe02ee3a256587f
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/various_ir_values_dbgrecords.test
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
[RemoveDIs] Update update_test_checks script to recognize dbg_records (#87388)
As we've added new IR elements for the RemoveDIs project,
we need the update_test_checks script to understand them. For the
records themselves this is already done automatically, but their
metadata arguments are not recognized as such due to lacking the
`metadata` prefix, which means they won't be checked by the script. This
patch fixes this by adding a check for all `![0-9]+` patterns as long as
they are not at the start of a line (which avoids matching global
values).
Commit: 792d437b56adfb3416daf8105942d4899fb82763
https://github.com/llvm/llvm-project/commit/792d437b56adfb3416daf8105942d4899fb82763
Author: NagyDonat <donat.nagy at ericsson.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/bugprone/sizeof-expression.rst
Log Message:
-----------
[clang-tidy NFC] Fix a typo in docs for sizeof-expression (#88912)
"Till heaven and earth pass, one jot, or one tittle shall not pass of
the law"
Commit: 5f3e106de3cd5ce6d7ba37fb11f6ad740cb430c5
https://github.com/llvm/llvm-project/commit/5f3e106de3cd5ce6d7ba37fb11f6ad740cb430c5
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
A lldb/test/API/commands/process/detach-resumes/Makefile
A lldb/test/API/commands/process/detach-resumes/TestDetachResumes.py
A lldb/test/API/commands/process/detach-resumes/main.cpp
M lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py
Log Message:
-----------
[lldb/linux] Make sure the process continues running after a detach (#88494)
Fixes #85084
Whenever an inferior thread stops, lldb-server sends a SIGSTOP to all
other threads in the process to force them to stop as well. If those
threads stop on their own before they get a signal, this SIGSTOP will
remain pending and be delivered the next time the process resumes.
Normally, this is not a problem, because lldb-server will detect this
stale SIGSTOP and resume the process. However, if we detach from the
process while it has these SIGSTOPs pending, they will get immediately
delivered, and the process will remain stopped (most likely forever).
This patch fixes that by sending a SIGCONT just before detaching from
the process. This signal cancels out any pending SIGSTOPs, and ensures
it is able to run after we detach. It does have one somewhat unfortunate
side-effect that in that the process's SIGCONT handler (if it has one)
will get executed spuriously (from the process's POV).
This could be _sometimes_ avoided by tracking which threads got send a
SIGSTOP, and whether those threads stopped due to it. From what I could
tell by observing its behavior, this is what gdb does. I have not tried
to replicate that behavior here because it adds a nontrivial amount of
complexity and the result is still uncertain -- we still need to send a
SIGCONT (and execute the handler) when any thread stops for some other
reason (and leaves our SIGSTOP hanging). Furthermore, since SIGSTOPs
don't stack, it's also possible that our SIGSTOP/SIGCONT combination
will cancel a genuine SIGSTOP being sent to the debugger application (by
someone else), and there is nothing we can do about that. For this
reason I think it's simplest and most predictible to just always send a
SIGCONT when detaching, but if it turns out this is breaking something,
we can consider implementing something more elaborate.
One alternative I did try is to use PTRACE_INTERRUPT to suspend the
threads instead of a SIGSTOP. PTRACE_INTERUPT requires using
PTRACE_SEIZE to attach to the process, which also made this solution
somewhat complicated, but the main problem with that approach is that
PTRACE_INTERRUPT is not considered to be a signal-delivery-stop, which
means it's not possible to resume it while injecting another signal to
the inferior (which some of our tests expect to be able to do). This
limitation could be worked around by forcing the thread into a signal
delivery stop whenever we need to do this, but this additional
complication is what made me think this approach is also not worthwhile.
This patch should fix (at least some of) the problems with
TestConcurrentVFork, but I've also added a dedicated test for checking
that a process keeps running after we detach. Although the problem I'm
fixing here is linux-specific, the core functinoality of not stopping
after a detach should function the same way everywhere.
Commit: c8dca5bc0733e2fba81008fc33fcad1f45ba666a
https://github.com/llvm/llvm-project/commit/c8dca5bc0733e2fba81008fc33fcad1f45ba666a
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP][Lower] Refactor lowering of compound constructs (#87070)
This patch simplifies the lowering from PFT to MLIR of OpenMP compound
constructs (i.e. combined and composite).
The new approach consists of iteratively processing the outermost leaf
construct of the given combined construct until it cannot be split
further. Both leaf constructs and composite ones have `gen...()`
functions that are called when appropriate.
This approach enables treating a leaf construct the same way regardless
of if it appeared as part of a combined construct, and it also enables
the lowering of composite constructs as a single unit.
Previous corner cases are now handled in a more straightforward way and
comments pointing to the relevant spec section are added. Directive sets
are also completed with missing LOOP related constructs.
Commit: 06eedffe0d2782922e63cc25cb927f4acdaf7b30
https://github.com/llvm/llvm-project/commit/06eedffe0d2782922e63cc25cb927f4acdaf7b30
Author: NagyDonat <donat.nagy at ericsson.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/ContainerModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugContainerModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugIteratorModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/IteratorModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/IteratorRangeChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/STLAlgorithmModeling.cpp
Log Message:
-----------
[analyzer] Use explicit call description mode in iterator checkers (#88913)
This commit explicitly specifies the matching mode (C library function,
any non-method function, or C++ method) for the `CallDescription`s
constructed in the iterator/container checkers.
This change won't cause major functional changes, but isn't NFC because
it ensures that e.g. call descriptions for a non-method function won't
accidentally match a method that has the same name.
Separate commits will perform (or have already performed) this change in
other checkers. My goal is to ensure that the call description mode is
always explicitly specified and eliminate (or strongly restrict) the
vague "may be either a method or a simple function" mode that's the
current default.
I'm handling the iterator checkers in this separate commit because
they're infamously complex; but I don't expect any trouble because this
transition doesn't interact with the "central" logic of iterator
handling.
Commit: 631c5e818ef8bb0f61fd3bb44cc4449be2142e2b
https://github.com/llvm/llvm-project/commit/631c5e818ef8bb0f61fd3bb44cc4449be2142e2b
Author: MbjYjbpivj <mbjyjbpivj at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir/IR/CommonAttrConstraints.td
Log Message:
-----------
[mlir] fix intNEQValue summary (#89029)
Fix the summary of intNEQValue.
Commit: d57907d0b4f292f148310695ed011fe5a0585d6b
https://github.com/llvm/llvm-project/commit/d57907d0b4f292f148310695ed011fe5a0585d6b
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libcxx/include/__algorithm/pstl_any_all_none_of.h
M libcxx/include/__algorithm/pstl_copy.h
M libcxx/include/__algorithm/pstl_count.h
M libcxx/include/__algorithm/pstl_equal.h
M libcxx/include/__algorithm/pstl_fill.h
M libcxx/include/__algorithm/pstl_find.h
M libcxx/include/__algorithm/pstl_for_each.h
M libcxx/include/__algorithm/pstl_generate.h
M libcxx/include/__algorithm/pstl_is_partitioned.h
M libcxx/include/__algorithm/pstl_merge.h
M libcxx/include/__algorithm/pstl_move.h
M libcxx/include/__algorithm/pstl_replace.h
M libcxx/include/__algorithm/pstl_rotate_copy.h
M libcxx/include/__algorithm/pstl_sort.h
M libcxx/include/__algorithm/pstl_stable_sort.h
M libcxx/include/__algorithm/pstl_transform.h
M libcxx/include/__iterator/cpp17_iterator_concepts.h
M libcxx/include/__numeric/pstl_reduce.h
M libcxx/include/__numeric/pstl_transform_reduce.h
M libcxx/test/libcxx/algorithms/cpp17_iterator_concepts.verify.cpp
A libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/support/test_iterators.h
Log Message:
-----------
[libc++] Add missing iterator requirement checks in the PSTL (#88127)
Also add tests for those, and add a few missing requirements to testing
iterators in the test suite.
Commit: 6c7853080451a7f9ba612f57b41a076061b2a1a9
https://github.com/llvm/llvm-project/commit/6c7853080451a7f9ba612f57b41a076061b2a1a9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
Log Message:
-----------
[X86] vector-shuffle-combining-sse41.ll - add missing AVX1/2/512 check prefixes
Commit: 37b26bf48b9894ed0c13fd1aede23472660fb75e
https://github.com/llvm/llvm-project/commit/37b26bf48b9894ed0c13fd1aede23472660fb75e
Author: Oleksandr "Alex" Zinenko <zinenko at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/test/Dialect/Transform/test-pattern-application.mlir
Log Message:
-----------
[mlir] transform.apply_patterns support more config options (#88484)
Greedy rewrite driver has options to control the number of rewrites
applies. Expose those via the corresponding transform op.
Commit: 4536ad47579d8d61f372ab85128bcfaed58a1256
https://github.com/llvm/llvm-project/commit/4536ad47579d8d61f372ab85128bcfaed58a1256
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Fix clang-tidy warning about else after return. NFC
Commit: 86a78284e7ce2ecc7a9283c7d141566a32371492
https://github.com/llvm/llvm-project/commit/86a78284e7ce2ecc7a9283c7d141566a32371492
Author: Quentin Dian <dianqk at dianqk.net>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/TailDuplicator.cpp
A llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir
Log Message:
-----------
[TailDuplicator] Add maximum predecessors and successors to consider tail duplicating blocks (#78582)
Fixes #78578.
Duplicating a BB which has both multiple predecessors and successors
will result in a complex CFG and also may cause huge amount of PHI
nodes. See
https://github.com/llvm/llvm-project/issues/78578#issuecomment-1962363580
for a detailed description of the limit.
Commit: 915c84b1480bb3c6d2e44ca83822d2c2304b763a
https://github.com/llvm/llvm-project/commit/915c84b1480bb3c6d2e44ca83822d2c2304b763a
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M lldb/source/Expression/IRExecutionUnit.cpp
Log Message:
-----------
[lldb] Fix evaluation of expressions with static initializers (#89063)
After 281d71604f418eb952e967d9dc4b26241b7f96a, llvm generates 32-bit
relocations, which overflow when we load these objects into high memory.
Interestingly, setting the code model to "large" does not help here
(perhaps it is the default?). I'm not completely sure that this is the
right thing to do, but it doesn't seem to cause any ill effects. I'll
follow up with the author of that patch about the expected behavior
here.
Commit: 79726ef5d20f3bf6510b67d7dd3378b8a41db768
https://github.com/llvm/llvm-project/commit/79726ef5d20f3bf6510b67d7dd3378b8a41db768
Author: Kevin P. Neal <kevin.neal at sas.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.h
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/IR/Function.cpp
A llvm/test/CodeGen/Generic/expand-vp-fp-intrinsics.ll
Log Message:
-----------
[VP] Correct lowering of predicated fma and faddmul to avoid strictfp. (#85272)
Correct missing cases in a switch that result in @llvm.vp.fma.v4f32
getting lowered to a constrained fma intrinsic. Vector predicated
lowering to contrained intrinsics is not supported currently, and
there's no consensus on the path forward. We certainly shouldn't be
introducing constrained intrinsics into a function that isn't strictfp.
Problem found with D146845.
Commit: 7b8625ec16efcb6d11e14a80e08c65dbfe68db9f
https://github.com/llvm/llvm-project/commit/7b8625ec16efcb6d11e14a80e08c65dbfe68db9f
Author: Fabian Ritter <fabian.ritter at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
Log Message:
-----------
[AMDGPU][Docs] Fix broken link to HRF memory model reference (#88696)
The link to the Heterogeneous-race-free Memory Models ASPLOS'14 paper by
Hower et al. pointed to a bogus website, probably because the domain
ownership has changed.
This patch updates it to a version hosted on research.cs.wisc.edu.
Commit: 971ec1f0eea324d4a1eec6709e2c97e1798a6002
https://github.com/llvm/llvm-project/commit/971ec1f0eea324d4a1eec6709e2c97e1798a6002
Author: DianQK <dianqk at dianqk.net>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Transforms/Inline/inline-switch-default-2.ll
Log Message:
-----------
[Inline] Regenerate inline-switch-default-2.ll (NFC)
Commit: 73140daebbf522dbb14dc4b2f3c67dc0aa1a62dd
https://github.com/llvm/llvm-project/commit/73140daebbf522dbb14dc4b2f3c67dc0aa1a62dd
Author: Oleksandr "Alex" Zinenko <zinenko at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/Transform/Interpreter.h
M mlir/lib/Bindings/Python/TransformInterpreter.cpp
M mlir/lib/CAPI/Dialect/TransformInterpreter.cpp
M mlir/python/mlir/dialects/transform/interpreter/__init__.py
M mlir/test/python/dialects/transform_interpreter.py
Log Message:
-----------
[mlir] expose transform dialect symbol merge to python (#87690)
This functionality is available in C++, make it available in Python
directly to operate on transform modules.
Commit: 20d653fdb2d4d6eafa4575cd954beaf7ecad113a
https://github.com/llvm/llvm-project/commit/20d653fdb2d4d6eafa4575cd954beaf7ecad113a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterPressure.cpp
Log Message:
-----------
[LLVM][CodeGen] Fix register lane liveness tracking in RegisterPressure (#88892)
Re-enable an old assertion in `decreaseSetPressure`.
Commit: 1fc72dbc807fb138cafd05501e2e31beaa574693
https://github.com/llvm/llvm-project/commit/1fc72dbc807fb138cafd05501e2e31beaa574693
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Log Message:
-----------
[RISCV] Add test for doLocalPostpass issue not checking if VL was modified. NFC
Commit: 76ad2897480a85532eee93daf041246881772693
https://github.com/llvm/llvm-project/commit/76ad2897480a85532eee93daf041246881772693
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/PowerPC/P10InstrResources.td
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCMacroFusion.def
M llvm/test/CodeGen/PowerPC/toc-data.ll
Log Message:
-----------
[PowerPC] 32-bit large code-model support for toc-data (#85129)
This patch adds the pseudo op ADDItocL for 32-bit large code-model
support for toc-data.
Commit: edbeae373489a2e710f328ceba50b4740c738217
https://github.com/llvm/llvm-project/commit/edbeae373489a2e710f328ceba50b4740c738217
Author: Luke Lau <luke at igalia.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Log Message:
-----------
[RISCV] Explicitly bail if something modifies VL/VTYPE in doLocalPostpass
If an instruction between MI and NextMI uses VL or VTYPE we demand the
respective fields so as to not clobber them at their uses. But we don't
consider if something might modify VL or VTYPE, and will happily coalesce
two vsetvlis when we need to preserve them.
This fixes this by skipping to the next vsetvli. Demanding the fields isn't
enough, as we need to preserve the VL and VTYPE values even if no fields
are demanded.
In practice this doesn't happen, presumably due to there not being any
instructions that write to VL or VTYPE without reading them. But I noticed
this whilst working on a separate patch and split it out.
Commit: 38205717501237f2b7a57eaabe65a8367e5f91c3
https://github.com/llvm/llvm-project/commit/38205717501237f2b7a57eaabe65a8367e5f91c3
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
[C99] Remove WG14 N522 from the C status page
This paper is about type compatibility rules that changed in C99, but
this is only applicable across translation units and so there's nothing
for us to test. The specific change was that C89 allowed different tag
types (e.g., struct and union) to be compatible and C99 tightened that
restriction. This is a case where the user gets whatever they get if
they link two TUs with incompatible tag types.
Commit: 41b7341d6b27adf81262a5a0bd4e430675b73bbb
https://github.com/llvm/llvm-project/commit/41b7341d6b27adf81262a5a0bd4e430675b73bbb
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Factor out helper to recursively collect all users (NFCI).
Factor out logic to collect all users recursively to be re-used
in https://github.com/llvm/llvm-project/pull/87816.
Commit: 856d1c44103f09f2ed0448001de9dcda63055733
https://github.com/llvm/llvm-project/commit/856d1c44103f09f2ed0448001de9dcda63055733
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-atomics.ll
Log Message:
-----------
[AMDGPU] Fix predicates for BUFFER_ATOMIC_FMIN/FMAX patterns (#89066)
Use OtherPredicates to avoid interfering with other uses of
SubtargetPredicate for GFX12.
Commit: 4f88c2311130791cf69da34b743b1b3ba7584a7b
https://github.com/llvm/llvm-project/commit/4f88c2311130791cf69da34b743b1b3ba7584a7b
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/NVGPU.h
A mlir/lib/Bindings/Python/DialectNVGPU.cpp
M mlir/lib/CAPI/Dialect/NVGPU.cpp
M mlir/python/CMakeLists.txt
M mlir/python/mlir/dialects/nvgpu.py
M mlir/test/python/dialects/nvgpu.py
Log Message:
-----------
[mlir][py] Add NVGPU's `TensorMapDescriptorType` in py bindings (#88855)
This PR adds NVGPU dialects' TensorMapDescriptorType in the py bindings.
This is a follow-up issue from [this
PR](https://github.com/llvm/llvm-project/pull/87153#discussion_r1546193095)
Commit: fda04b1caaf1a61b208f23e717a2db6d9b861f5a
https://github.com/llvm/llvm-project/commit/fda04b1caaf1a61b208f23e717a2db6d9b861f5a
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libc/examples/README.md
M libc/examples/examples.cmake
Log Message:
-----------
[libc] Replace mentions of `LIBC_FULLBUILD` with `LLVM_LIBC_FULL_BUILD` in 'examples/' (#88657)
Resolves #88328
Commit: d558c090fc78beb6737098f058a084635b893567
https://github.com/llvm/llvm-project/commit/d558c090fc78beb6737098f058a084635b893567
Author: yronglin <yronglin777 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/include/clang/Sema/ParsedAttr.h
Log Message:
-----------
[NFC] Clean dead code in ParsedAttr.h (#89064)
Signed-off-by: yronglin <yronglin777 at gmail.com>
Commit: dbafcd7e6d5b6c3aff74307b2ed5ee1834f275b0
https://github.com/llvm/llvm-project/commit/dbafcd7e6d5b6c3aff74307b2ed5ee1834f275b0
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M lldb/test/API/commands/process/detach-resumes/TestDetachResumes.py
Log Message:
-----------
[lldb] XFAIL TestDetachResumes on windows
Commit: e49043512dbdc68319093da46e95a1e331ef837e
https://github.com/llvm/llvm-project/commit/e49043512dbdc68319093da46e95a1e331ef837e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/bitreverse-codesize.ll
M llvm/test/Analysis/CostModel/X86/bitreverse-latency.ll
M llvm/test/Analysis/CostModel/X86/bitreverse-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/bitreverse.ll
Log Message:
-----------
[CostModel][X86] Update BITREVERSE costs for GFNI targets
Inspired by the recent patches by @shamithoke - we have real scheduler model numbers for GFNI instructions now, allowing us to calculate an upper bounds costs table instead of performing it analytically.
Commit: 4a5ab13bf5a94ec7f0eabaf24dfe1a5ee720b860
https://github.com/llvm/llvm-project/commit/4a5ab13bf5a94ec7f0eabaf24dfe1a5ee720b860
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
Log Message:
-----------
[VectorCombine] Remove single quotes from "-passes=vector-combine"
These confuse the update_test_checks.py script when run by DOS cmd.exe
Commit: 5d314353fbec1a15cd8900f466dcdcf2af40e8c9
https://github.com/llvm/llvm-project/commit/5d314353fbec1a15cd8900f466dcdcf2af40e8c9
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Check for VPWidenLoadRecipe directly in truncateToMinBW. (NFCI).
Since ne
After a separate recipe has been introduced for wide loads in
a9bafe91dd0, we can directly check for load recipes in the early
bail-out and remove the redundant bail out for stores.
Commit: 812963f6aa2adb5e990f273b8ce1a0eabcdefd7f
https://github.com/llvm/llvm-project/commit/812963f6aa2adb5e990f273b8ce1a0eabcdefd7f
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libcxx/include/__chrono/formatter.h
M libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.nonmembers/ostream.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.system/sys_date.ostream.pass.cpp
M libcxx/test/std/time/time.syn/formatter.year_month_day.pass.cpp
Log Message:
-----------
[libc++][chrono] Improves date formatting. (#86127)
The formatting of years has been done manually since the results of %Y
outside the "typical" range may produce unexpected values. The same
applies to %F which is identical to %Y-%m-%d. None of these conversion
specifiers is affected by the locale used. So it's trivial to manually
handle this case.
This removes several platform specific ifdefs from the tests.
Commit: 458328ae23d318a5055d5bac66426b8551bce01f
https://github.com/llvm/llvm-project/commit/458328ae23d318a5055d5bac66426b8551bce01f
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/include/clang/Sema/Lookup.h
A clang/include/clang/Sema/Redeclaration.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/InterpreterUtils.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Log Message:
-----------
[clang][NFC] Refactor `Sema::RedeclarationKind`
This patch converts the enum into scoped enum, and moves it into its own header for the time being. It's definition is needed in `Sema.h`, and is going to be needed in upcoming `SemaObjC.h`. `Lookup.h` can't hold it, because it includes `Sema.h`.
Commit: 950bb097e11d6ee26533c00519c62df994322228
https://github.com/llvm/llvm-project/commit/950bb097e11d6ee26533c00519c62df994322228
Author: Dinar Temirbulatov <Dinar.Temirbulatov at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
M clang/test/Sema/aarch64-sme-func-attrs.c
Log Message:
-----------
Revert "[Clang][AArch64] Warn when calling non/streaming about vector size difference (#79842)"
This reverts commit 4e85e1ffcaf161736e27a24c291c1177be865976
Commit: b854a2323337be2633b1135f590678a17e9d1ade
https://github.com/llvm/llvm-project/commit/b854a2323337be2633b1135f590678a17e9d1ade
Author: Robin Caloudis <robin.caloudis at gmx.de>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/arm/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/docs/c23.rst
M libc/docs/fenv.rst
M libc/spec/stdc.td
M libc/src/fenv/CMakeLists.txt
A libc/src/fenv/fetestexceptflag.cpp
A libc/src/fenv/fetestexceptflag.h
M libc/test/src/fenv/CMakeLists.txt
M libc/test/src/fenv/exception_flags_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
Log Message:
-----------
[libc][c23][fenv] Implement fetestexceptflag (#87828)
Provide C23 `fetestexceptflag` function according to 7.6.4.6 in the
latest [revision of the C
standard](https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3096.pdf)
from 2023-04-02.
Closes https://github.com/llvm/llvm-project/issues/87565.
Commit: 8656d4c6a7a742c6fa6ee02c2ace7415163e65e4
https://github.com/llvm/llvm-project/commit/8656d4c6a7a742c6fa6ee02c2ace7415163e65e4
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/lib/Parse/ParseDecl.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p6-cxx23.cpp
Log Message:
-----------
[Clang][Parse] Diagnose requires expressions with explicit object parameters (#88974)
Clang currently allows the following:
```
auto x = requires (this int) { true; };
```
This patch addresses that.
Commit: abd5e45a96954d80f6ffe6d8676c0059fae8573b
https://github.com/llvm/llvm-project/commit/abd5e45a96954d80f6ffe6d8676c0059fae8573b
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/sanitizer_atomic.h
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang.h
R compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_mips.h
R compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_other.h
R compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_x86.h
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_msvc.h
M llvm/utils/gn/secondary/compiler-rt/lib/sanitizer_common/BUILD.gn
Log Message:
-----------
[compiler-rt] Use __atomic builtins whenever possible
The code in this file dates back to 2012 when Clang's support for atomic
builtins was still quite limited. The bugs referenced in the comment
at the top of the file have long been fixed and using the compiler
builtins directly should now generate slightly better code.
Additionally, this allows using the atomic builtin header for platforms
where the __sync_builtins are lacking (e.g. Arm Morello).
This change does not introduce any code generation changes for
__tsan_read*/__tsan_write* or __tsan_func_{entry,exit} on x86, which
indicates the previously noted compiler issues have been fixed.
We also have to touch the non-clang codepaths here since the only way we
can make this work easily is by making the memory_order enum match the
compiler-provided macros, so we have to update the debug checks that
assumed the enum was always a bitflag.
The one downside of this change is that 32-bit MIPS now definitely
requires libatomic (but that may already have been needed for RMW ops).
Reviewed By: dvyukov
Pull Request: https://github.com/llvm/llvm-project/pull/84439
Commit: a88ea8fbb3953c2fe2887438baf342e381a79d8b
https://github.com/llvm/llvm-project/commit/a88ea8fbb3953c2fe2887438baf342e381a79d8b
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/cuf-invalid.fir
Log Message:
-----------
[flang][cuda] Update memory effect on fir.cuda_allocate op (#88930)
Add MemRead effect on the box operand as the descriptor might be read
when performing the allocation of the data.
Also update the expected type of the box operand to be a reference.
Check in the verifier that this is a reference to a box or class type.
This addresses the comment made post commit on #88586
Commit: da70f2cdcde8cb96e75ce0236db1fb5353407a69
https://github.com/llvm/llvm-project/commit/da70f2cdcde8cb96e75ce0236db1fb5353407a69
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/lib/Lower/Allocatable.cpp
A flang/test/Lower/CUDA/cuda-allocatable.cuf
Log Message:
-----------
[flang][cuda] Lower ALLOCATE for device variable (#88980)
Replace the runtime call to `AllocatableAllocate` for CUDA device
variable to the newly added `fir.cuda_allocate` operation.
Commit: 19c6a7feca6e1558ef7cbe18efd2477c1126899d
https://github.com/llvm/llvm-project/commit/19c6a7feca6e1558ef7cbe18efd2477c1126899d
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/test/CodeGen/aarch64-cpu-supports.c
M clang/test/CodeGen/aarch64-mixed-target-attributes.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/attr-target-clones-aarch64.c
M clang/test/Sema/attr-target-version.c
M clang/test/SemaCXX/attr-target-version.cpp
M compiler-rt/lib/builtins/cpu_model/aarch64.c
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/fuchsia.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
Log Message:
-----------
[FMV] Remove useless features according the latest ACLE spec. (#88965)
As explained in https://github.com/ARM-software/acle/pull/315 we
are deprecating features which aren't adding any value. These are:
sha1, pmull, dit, dgh, ebf16, sve-bf16, sve-ebf16, sve-i8mm,
sve2-pmull128, memtag2, memtag3, ssbs2, bti, ls64_v, ls64_accdata
Commit: 06947b9f8d258fe66fc69f1e7c0197cb621da3a5
https://github.com/llvm/llvm-project/commit/06947b9f8d258fe66fc69f1e7c0197cb621da3a5
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libc/config/linux/api.td
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/pthread_condattr_t.h
M libc/include/pthread.h.def
M libc/spec/posix.td
M libc/src/pthread/CMakeLists.txt
A libc/src/pthread/pthread_condattr_destroy.cpp
A libc/src/pthread/pthread_condattr_destroy.h
A libc/src/pthread/pthread_condattr_getclock.cpp
A libc/src/pthread/pthread_condattr_getclock.h
A libc/src/pthread/pthread_condattr_getpshared.cpp
A libc/src/pthread/pthread_condattr_getpshared.h
A libc/src/pthread/pthread_condattr_init.cpp
A libc/src/pthread/pthread_condattr_init.h
A libc/src/pthread/pthread_condattr_setclock.cpp
A libc/src/pthread/pthread_condattr_setclock.h
A libc/src/pthread/pthread_condattr_setpshared.cpp
A libc/src/pthread/pthread_condattr_setpshared.h
M libc/test/src/pthread/CMakeLists.txt
A libc/test/src/pthread/pthread_condattr_test.cpp
Log Message:
-----------
[libc][POSIX][pthreads] implement pthread_condattr_t functions (#88987)
Implement:
- pthread_condattr_destroy
- pthread_condattr_getclock
- pthread_condattr_getpshared
- pthread_condattr_init
- pthread_condattr_setclock
- pthread_condattr_setpshared
Fixes: #88581
Commit: 4edeaffbf255137861f5153eb1a6183d956efede
https://github.com/llvm/llvm-project/commit/4edeaffbf255137861f5153eb1a6183d956efede
Author: fabrizio-indirli <fabrizio.indirli at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir
Log Message:
-----------
[mlir][tosa] Fix tosa.Resize-to-linalg lowering (#88514)
Commit: 564f9abfcc3b99a01843f88b5a2c7309bfab5a33
https://github.com/llvm/llvm-project/commit/564f9abfcc3b99a01843f88b5a2c7309bfab5a33
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir] Add missing dep after 4f88c2311130791cf69da34b743b1b3ba7584a7b
Commit: e59632bdfd4c70caed437216af17d335858686fd
https://github.com/llvm/llvm-project/commit/e59632bdfd4c70caed437216af17d335858686fd
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVScheduleV.td
Log Message:
-----------
[RISCV] Fix typo in RISCVScheduleV.td that was introduced in 60a1158
Commit: 676d3bafc09d0c331a04b813804407334de12917
https://github.com/llvm/llvm-project/commit/676d3bafc09d0c331a04b813804407334de12917
Author: Jorge Gorbe Moya <jgorbe at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel][libc] Add missing dep after b854a2323337be2633b1135f590678a17e9d1ade
Commit: 693a458287d019c5c6a66fe3019d099df2978cdb
https://github.com/llvm/llvm-project/commit/693a458287d019c5c6a66fe3019d099df2978cdb
Author: Abdul Raheem <55028856+abdulraheembeigh at users.noreply.github.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M mlir/include/mlir/Interfaces/ViewLikeInterface.td
Log Message:
-----------
[MLIR] Update doc comment in ViewLikeInterface.td (NFC) (#89074)
Signed-off: Abdul Raheem Beigh <abdulraheembeigh at gmail.com>
Commit: 6f7160eedb2db02f37d4ffd52fff7b0cf88b3fdc
https://github.com/llvm/llvm-project/commit/6f7160eedb2db02f37d4ffd52fff7b0cf88b3fdc
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
Log Message:
-----------
[SLP]Attempt to vectorize long stores, if short one failed.
We can try to vectorize long store sequences, if short ones were
unsuccessful because of the non-profitable vectorization. It should not
increase compile time significantly (stores are sorted already,
complexity is n x log n), but vectorize extra code.
Metric: size..text
Program size..text
results results0 diff
test-suite :: External/SPEC/CINT2006/400.perlbench/400.perlbench.test 1088012.00 1088236.00 0.0%
test-suite :: SingleSource/UnitTests/matrix-types-spec.test 480396.00 480476.00 0.0%
test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 664613.00 664661.00 0.0%
test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 664613.00 664661.00 0.0%
test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 2041105.00 2040961.00 -0.0%
test-suite :: MultiSource/Applications/JM/lencod/lencod.test 836563.00 836387.00 -0.0%
test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 1035100.00 1032140.00 -0.3%
In all benchmarks extra code gets vectorized
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/88563
Commit: eefee382186005d3662958e076c8e61e286ea1ab
https://github.com/llvm/llvm-project/commit/eefee382186005d3662958e076c8e61e286ea1ab
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libc/src/pthread/pthread_condattr_destroy.cpp
M libc/test/src/pthread/CMakeLists.txt
Log Message:
-----------
[libc] set cmake dependencies for condattr test (#89103)
The entrypoints are not yet exposed on non-x86. Express this dependency
to
unbreak post submit.
Fixes #88987
Commit: 825536039d667eeb933c590fe40c358fdea03a8d
https://github.com/llvm/llvm-project/commit/825536039d667eeb933c590fe40c358fdea03a8d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
Log Message:
-----------
[CostModel][X86] Add basic GFNI target test coverage for shift/rotate costs
Commit: da04e4afd3cae13581cac85688fbf10a5848655f
https://github.com/llvm/llvm-project/commit/da04e4afd3cae13581cac85688fbf10a5848655f
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
Log Message:
-----------
[InstCombine] Use `auto *` instead of `auto` in `visitSIToFP`; NFC
Commit: d423d80e560d8bf7ca493596d9f34a9e1f0eede7
https://github.com/llvm/llvm-project/commit/d423d80e560d8bf7ca493596d9f34a9e1f0eede7
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libcxx/CMakeLists.txt
M libcxx/cmake/caches/Apple.cmake
M libcxx/include/CMakeLists.txt
R libcxx/include/__algorithm/pstl_backend.h
R libcxx/include/__algorithm/pstl_backends/cpu_backend.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/any_of.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/backend.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/fill.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/find_if.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/for_each.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/libdispatch.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/merge.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/serial.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/stable_sort.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/thread.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/transform.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/transform_reduce.h
M libcxx/include/__algorithm/pstl_copy.h
M libcxx/include/__algorithm/pstl_count.h
M libcxx/include/__algorithm/pstl_find.h
M libcxx/include/__algorithm/pstl_for_each.h
M libcxx/include/__algorithm/pstl_generate.h
M libcxx/include/__algorithm/pstl_is_partitioned.h
M libcxx/include/__algorithm/pstl_merge.h
M libcxx/include/__algorithm/pstl_move.h
M libcxx/include/__algorithm/pstl_replace.h
M libcxx/include/__algorithm/pstl_rotate_copy.h
M libcxx/include/__algorithm/pstl_sort.h
M libcxx/include/__algorithm/pstl_stable_sort.h
M libcxx/include/__algorithm/pstl_transform.h
M libcxx/include/__config_site.in
M libcxx/include/__numeric/pstl_transform_reduce.h
A libcxx/include/__pstl/backends/libdispatch.h
A libcxx/include/__pstl/backends/serial.h
A libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/configuration.h
A libcxx/include/__pstl/configuration_fwd.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap
M libcxx/src/CMakeLists.txt
M libcxx/src/pstl/libdispatch.cpp
M libcxx/test/libcxx/algorithms/pstl.libdispatch.chunk_partitions.pass.cpp
M libcxx/test/libcxx/vendor/apple/system-install-properties.sh.cpp
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++][pstl] Promote CPU backends to top-level backends (#88968)
This patch removes the two-level backend dispatching mechanism we had in
the PSTL. Instead of selecting both a PSTL backend and a PSTL CPU
backend, we now only select a top-level PSTL backend. This greatly
simplifies the PSTL configuration layer.
While this patch technically removes some flexibility from the PSTL
configuration mechanism because CPU backends are not considered
separately, it opens the door to a much more powerful configuration
mechanism based on chained backends in a follow-up patch.
This is a step towards overhauling the PSTL dispatching mechanism.
Commit: 8d49ce176414cd4d0d5d276fd721d9226e17e810
https://github.com/llvm/llvm-project/commit/8d49ce176414cd4d0d5d276fd721d9226e17e810
Author: David Green <david.green at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td
M llvm/test/TableGen/GlobalISelEmitter.td
Log Message:
-----------
[GlobalISel][AArch64] Add LLRINT support (#88702)
This hooks up G_INTRINSIC_LLRINT instructions, very similar to the lrint
nodes that already exist. On AArch64 they are treated the same as lrint
with the default return types.
Commit: 2c22a0c16d1cb844eac142156ba67098627a336c
https://github.com/llvm/llvm-project/commit/2c22a0c16d1cb844eac142156ba67098627a336c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/sub-xor.ll
Log Message:
-----------
[InstCombine] Add test case for turning sub into xor using dominating condition. NFC
I plan to disable using dominating conditions for turning sub into
xor, but first we need that demonstrates it currently happens.
Commit: 421a8c5892b7e59f27b2c21452f81fa789a758fd
https://github.com/llvm/llvm-project/commit/421a8c5892b7e59f27b2c21452f81fa789a758fd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
Log Message:
-----------
[InstCombine] Add phase ordering test for #88239. NFC
Commit: ed741ffe893698cd14c6785ac2ee7031d9d344a6
https://github.com/llvm/llvm-project/commit/ed741ffe893698cd14c6785ac2ee7031d9d344a6
Author: Nathan Lanza <nathanlanza at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[github] Add ClangIR to new-prs-labeler.yml (#86088)
Commit: c02ed29ec151d1d555c3735efef2ab215126ddbf
https://github.com/llvm/llvm-project/commit/c02ed29ec151d1d555c3735efef2ab215126ddbf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
Log Message:
-----------
[CostModel][X86] Recognise vector rotation by uniform constant patterns
Adds suitable costs for AVX512 targets (we still rely on default expansion for AVX2 and earlier)
Commit: 58a08e154c804051aaca9151a8053aea3ec15646
https://github.com/llvm/llvm-project/commit/58a08e154c804051aaca9151a8053aea3ec15646
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rv32zba.ll
M llvm/test/CodeGen/RISCV/rv64zba.ll
Log Message:
-----------
[RISCV] Add coverage for strength reduction of mul by small negative immediates
Commit: cc82f1290a1e2157a6c0530d78d8cc84d2b8553d
https://github.com/llvm/llvm-project/commit/cc82f1290a1e2157a6c0530d78d8cc84d2b8553d
Author: Usman Nadeem <mnadeem at quicinc.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/load-insert-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-shift-neg.ll
M llvm/test/CodeGen/AArch64/predicated-add-sub.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
M llvm/test/CodeGen/AArch64/reassocmls.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/sat-add.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
M llvm/test/CodeGen/AArch64/sve-abd.ll
M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fcmp.ll
M llvm/test/CodeGen/AArch64/sve-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
M llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
M llvm/test/CodeGen/AArch64/sve-hadd.ll
M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
M llvm/test/CodeGen/AArch64/sve-insert-element.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-pr62151.ll
M llvm/test/CodeGen/AArch64/sve-pred-arith.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-stepvector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
M llvm/test/CodeGen/AArch64/sve2-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll
M llvm/test/CodeGen/AArch64/sve2-rsh.ll
M llvm/test/CodeGen/AArch64/sve2-xar.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
M llvm/test/CodeGen/AArch64/vec_uaddo.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
M llvm/test/CodeGen/AArch64/vector-gep.ll
M llvm/test/CodeGen/AArch64/vselect-constants.ll
M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
Log Message:
-----------
[AArch64] Update latencies for Cortex-A510 scheduling model (#87293)
Updated according to the Software Optimization Guide for Arm®
Cortex®‑A510 Core Revision: r1p3 Issue 6.0.
Commit: 4572a2db2c2c48820e79fb65f3810348371db4f1
https://github.com/llvm/llvm-project/commit/4572a2db2c2c48820e79fb65f3810348371db4f1
Author: David Green <david.green at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll
Log Message:
-----------
[AArch64] Add some test cases for LD2/LD3/LD4 shuffles. NFC
Commit: 5a0942cd7423069e78fdfb9743a13aedfa7bdee0
https://github.com/llvm/llvm-project/commit/5a0942cd7423069e78fdfb9743a13aedfa7bdee0
Author: Youngsuk Kim <joseph942010 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
M llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
Log Message:
-----------
[llvm][NVPTX] Don't emit unused var 'temp_param_reg' (NFC) (#89004)
Don't emit unused variable 'temp_param_reg' which has been around since
ae556d3ef72dfe5f40a337b7071f42b7bf5b66a4 .
Commit: 800f1050e190430f217e1fd0db9414dacc835e11
https://github.com/llvm/llvm-project/commit/800f1050e190430f217e1fd0db9414dacc835e11
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[GitHub] Add a new mapping for `offload` subproject (#89118)
Fix #89071.
Commit: 6f7976c883da592f2cf6bfadef152e4203c00445
https://github.com/llvm/llvm-project/commit/6f7976c883da592f2cf6bfadef152e4203c00445
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M libcxx/docs/Status/FormatPaper.csv
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/sys_info.h
M libcxx/include/chrono
A libcxx/test/libcxx/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
A libcxx/test/std/time/time.syn/formatter.sys_info.pass.cpp
A libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M libcxx/test/support/test_macros.h
Log Message:
-----------
[libc++][TZDB] Adds sys_info formatter. (#85896)
Implements parts of:
- P0355 Extending <chrono> to Calendars and Time Zones
- P1361 Integration of chrono with text formatting
Commit: b1dc62f139ef265a36a2a739ce9ba4e1e48a6dbe
https://github.com/llvm/llvm-project/commit/b1dc62f139ef265a36a2a739ce9ba4e1e48a6dbe
Author: Amirreza Ashouri <ar.ashouri999 at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M clang/lib/Parse/ParseExprCXX.cpp
M clang/test/Sema/static-assert.c
M clang/test/SemaCXX/builtins.cpp
M clang/test/SemaCXX/deprecated-builtins.cpp
Log Message:
-----------
[clang]Treat arguments to builtin type traits as template type arguments (#87132)
This change improves error messages for builtins in case of empty
parentheses.
Fixes llvm#86997
Commit: 6cea7c491f4c4c68aa0494a9b18f36ff40c22c81
https://github.com/llvm/llvm-project/commit/6cea7c491f4c4c68aa0494a9b18f36ff40c22c81
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/test/CodeGen/X86/code-model-elf.ll
Log Message:
-----------
[X86] Always use 64-bit relocations in no-PIC large code model (#89101)
This matches other types of relocations, e.g. to constant pool. And
makes things more consistent with PIC large code model.
Some users of the large code model may not place small data in the lower
2GB of the address space (e.g.
https://github.com/ClangBuiltLinux/linux/issues/2016), so just
unconditionally use 64-bit relocations in the large code model.
So now functions in a section not marked large will use 64-bit
relocations to reference everything when using the large code model.
This also fixes some lldb tests broken by #88172
(https://lab.llvm.org/buildbot/#/builders/68/builds/72458).
Commit: 1460b4964c7ada2f7536006722c8585b5bd0a1b5
https://github.com/llvm/llvm-project/commit/1460b4964c7ada2f7536006722c8585b5bd0a1b5
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Manually port d423d80e560d
Commit: db2f64ee1f743153f242ca92bf627458ba7f8000
https://github.com/llvm/llvm-project/commit/db2f64ee1f743153f242ca92bf627458ba7f8000
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
Log Message:
-----------
AMDGPU: Fix not handling atomicrmw fadd in exotic address spaces correctly
We try to interpret unknown address space numbers as aliases of global,
but this wasn't applied here. Also improve test coverage for the
buffer fat pointer address space.
Commit: 652bcf685c72447f3cc46d93d6c9c1948e8499f3
https://github.com/llvm/llvm-project/commit/652bcf685c72447f3cc46d93d6c9c1948e8499f3
Author: Matthias Braun <matze at braunis.de>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
A llvm/test/CodeGen/X86/codegen-prepare-addrmode-tls.ll
A llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-tls.ll
Log Message:
-----------
CodeGenPrepare: Add support for llvm.threadlocal.address address-mode sinking (#87844)
Depending on the TLSMode many thread-local accesses on x86 can be
expressed by adding a %fs: segment register to an addressing mode. Even
if there are mutliple users of a `llvm.threadlocal.address` intrinsic it
is generally not worth sharing the value in a register but instead fold
the %fs access into multiple addressing modes.
Hence this changes CodeGenPrepare to duplicate the
`llvm.threadlocal.address` intrinsic as necessary.
Introduces a new `TargetLowering::addressingModeSupportsTLS` callback
that allows targets to indicate whether TLS accesses can be part of an
addressing mode.
This is fixing a performance problem, as this folding of TLS-accesses
into multiple addressing modes happened naturally before the
introduction of the `llvm.threadlocal.address` intrinsic, but regressed
due to `SelectionDAG` keeping things in registers when accessed across
basic blocks, so CodeGenPrepare needs to duplicate to mitigate this. We
see a ~0.5% recovery in a codebase with heavy TLS usage (HHVM).
This fixes most of #87437
Commit: 2583b2eea4a509424e5e5f51dffedd9beede76a3
https://github.com/llvm/llvm-project/commit/2583b2eea4a509424e5e5f51dffedd9beede76a3
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/runtime/extensions.cpp
Log Message:
-----------
[flang][NFC] Add missing include for FreeBSD
Suggested by dankm here: https://github.com/llvm/llvm-project/pull/88517
Commit: d0c51f7d5496015ce410cc758a7caf976ffaaec7
https://github.com/llvm/llvm-project/commit/d0c51f7d5496015ce410cc758a7caf976ffaaec7
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/CodeGen/LivePhysRegs.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/MachineBasicBlock.cpp
Log Message:
-----------
[LiveIns] Improve recomputeLiveIns() (#88951)
Some small changes to recomputeLiveIns() to improve performance:
- Instead of copying the list of old live-ins, and then clearing
them, a new method swaps the list for an empty one.
- getLiveIns() now returns a constant reference to the list
As result, the list-data is never copied. Depending on the
implementation
details of the vector container, it can also save calls to allocate
and deallocate memory.
I see a small improvement on CTMark with these changes.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 60b90b523323f8196a9e4a68b1f33358624c09eb
https://github.com/llvm/llvm-project/commit/60b90b523323f8196a9e4a68b1f33358624c09eb
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py
Log Message:
-----------
[lldb][DynamicLoader] Fix lldb unable to stop at _dl_debug_state if user set it before the process launched. (#88792)
If user sets a breakpoint at `_dl_debug_state` before the process
launched, the breakpoint is not resolved yet. When lldb loads dynamic
loader module, it's created with `Target::GetOrCreateModule` which
notifies any pending breakpoint to resolve. However, the module's
sections are not loaded at this time. They are loaded after returned
from
[Target::GetOrCreateModule](https://github.com/llvm/llvm-project/blob/0287a5cc4e2a5ded1ae2e4079f91052e6a6b8d9b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp#L574-L577).
This change fixes it by manually resolving breakpoints after creating
dynamic loader module.
Commit: e15f47f2675a5400464aec00219658882df5e3fa
https://github.com/llvm/llvm-project/commit/e15f47f2675a5400464aec00219658882df5e3fa
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M llvm/include/llvm/Analysis/SimplifyQuery.h
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/test/Transforms/InstCombine/sub-xor.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
Log Message:
-----------
[InstCombine] Don't use dominating conditions to transform sub into xor. (#88566)
Other passes are unable to reverse this transform if we use dominating
conditions.
Fixes #88239.
Commit: f309c882ea5ad411ac1011a4228c0e49b1025bb4
https://github.com/llvm/llvm-project/commit/f309c882ea5ad411ac1011a4228c0e49b1025bb4
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/runtime/extensions.cpp
Log Message:
-----------
Revert "[flang][NFC] Add missing include for FreeBSD"
This reverts commit 2583b2eea4a509424e5e5f51dffedd9beede76a3.
Commit: 0cee89431d77d0bb0809fd9b2c9d21da2a2783aa
https://github.com/llvm/llvm-project/commit/0cee89431d77d0bb0809fd9b2c9d21da2a2783aa
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/runtime/extensions.cpp
Log Message:
-----------
[flang][NFC] Add missing include for FreeBSD
Suggested by dankm here: https://github.com/llvm/llvm-project/pull/88517
Commit: 9435edf628cb2011652897e1f10f7c55313d50be
https://github.com/llvm/llvm-project/commit/9435edf628cb2011652897e1f10f7c55313d50be
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M flang/lib/Lower/Allocatable.cpp
M flang/test/Lower/CUDA/cuda-allocatable.cuf
Log Message:
-----------
[flang][cuda] Lower DEALLOCATE for device variables (#89091)
Replace the runtime call to `AllocatableDeallocate` for CUDA device
variable to the newly added `fir.cuda_deallocate` operation.
This is similar with #88980
A third patch will handle the case of automatic dealloctaion of device
allocatable variables
Commit: b9c98dcc042e0fe956d9f9ef7ea6e7c4f190438f
https://github.com/llvm/llvm-project/commit/b9c98dcc042e0fe956d9f9ef7ea6e7c4f190438f
Author: Fangrui Song <i at maskray.me>
Date: 2024-04-17 (Wed, 17 Apr 2024)
Changed paths:
M .github/new-prs-labeler.yml
M clang-tools-extra/docs/clang-tidy/checks/bugprone/sizeof-expression.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Lookup.h
M clang/include/clang/Sema/ParsedAttr.h
A clang/include/clang/Sema/Redeclaration.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/Interpreter/InterpreterUtils.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseObjc.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaExprMember.cpp
M clang/lib/Sema/SemaExprObjC.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaPseudoObject.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Checkers/ContainerModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugContainerModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugIteratorModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/IteratorModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/IteratorRangeChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/STLAlgorithmModeling.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p6-cxx23.cpp
M clang/test/CodeGen/aarch64-cpu-supports.c
M clang/test/CodeGen/aarch64-mixed-target-attributes.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-version.c
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/aarch64-cpu-supports.c
M clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
M clang/test/Sema/aarch64-sme-func-attrs.c
M clang/test/Sema/attr-target-clones-aarch64.c
M clang/test/Sema/attr-target-version.c
M clang/test/Sema/static-assert.c
R clang/test/SemaCXX/PR41441.cpp
M clang/test/SemaCXX/attr-target-version.cpp
M clang/test/SemaCXX/builtins.cpp
M clang/test/SemaCXX/deprecated-builtins.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
M clang/www/c_status.html
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/lib/builtins/cpu_model/aarch64.c
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/fuchsia.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
M compiler-rt/lib/sanitizer_common/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/sanitizer_atomic.h
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang.h
R compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_mips.h
R compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_other.h
R compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_x86.h
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_msvc.h
M flang/include/flang/Lower/CallInterface.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Semantics/openmp-directive-sets.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/runtime/extensions.cpp
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Fir/cuf-invalid.fir
A flang/test/Lower/CUDA/cuda-allocatable.cuf
A flang/test/Lower/HLFIR/internal-procedures-bindc-host.f90
M flang/test/Lower/HLFIR/internal-procedures.f90
M flang/test/Lower/OpenACC/acc-routine04.f90
M flang/test/Lower/OpenMP/FIR/if-clause.f90
M flang/test/Lower/OpenMP/FIR/loop-combined.f90
M flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90
M flang/test/Lower/OpenMP/FIR/simd.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-combined.f90
M flang/test/Lower/OpenMP/parallel-private-clause.f90
M flang/test/Lower/OpenMP/simd.f90
M flang/test/Lower/OpenMP/threadprivate-hlfir.f90
M flang/test/Lower/OpenMP/threadprivate-host-association-2.f90
M flang/test/Lower/OpenMP/threadprivate-host-association.f90
M flang/test/Lower/character-elemental.f90
M flang/test/Lower/equivalence-with-host-assoc.f90
M flang/test/Lower/explicit-interface-results-2.f90
M flang/test/Lower/host-associated-functions.f90
M flang/test/Lower/host-associated-globals.f90
M flang/test/Lower/host-associated.f90
M flang/test/Lower/polymorphic.f90
A flang/test/Semantics/OpenMP/threadprivate07.f90
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/arm/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/docs/c23.rst
M libc/docs/fenv.rst
M libc/examples/README.md
M libc/examples/examples.cmake
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/pthread_condattr_t.h
M libc/include/pthread.h.def
M libc/spec/posix.td
M libc/spec/stdc.td
M libc/src/__support/macros/sanitizer.h
M libc/src/fenv/CMakeLists.txt
A libc/src/fenv/fetestexceptflag.cpp
A libc/src/fenv/fetestexceptflag.h
M libc/src/pthread/CMakeLists.txt
A libc/src/pthread/pthread_condattr_destroy.cpp
A libc/src/pthread/pthread_condattr_destroy.h
A libc/src/pthread/pthread_condattr_getclock.cpp
A libc/src/pthread/pthread_condattr_getclock.h
A libc/src/pthread/pthread_condattr_getpshared.cpp
A libc/src/pthread/pthread_condattr_getpshared.h
A libc/src/pthread/pthread_condattr_init.cpp
A libc/src/pthread/pthread_condattr_init.h
A libc/src/pthread/pthread_condattr_setclock.cpp
A libc/src/pthread/pthread_condattr_setclock.h
A libc/src/pthread/pthread_condattr_setpshared.cpp
A libc/src/pthread/pthread_condattr_setpshared.h
M libc/test/src/fenv/CMakeLists.txt
M libc/test/src/fenv/exception_flags_test.cpp
M libc/test/src/pthread/CMakeLists.txt
A libc/test/src/pthread/pthread_condattr_test.cpp
M libcxx/CMakeLists.txt
M libcxx/cmake/caches/Apple.cmake
M libcxx/docs/Status/FormatPaper.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/pstl_any_all_none_of.h
R libcxx/include/__algorithm/pstl_backend.h
R libcxx/include/__algorithm/pstl_backends/cpu_backend.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/any_of.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/backend.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/fill.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/find_if.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/for_each.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/libdispatch.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/merge.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/serial.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/stable_sort.h
R libcxx/include/__algorithm/pstl_backends/cpu_backends/thread.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/transform.h
M libcxx/include/__algorithm/pstl_backends/cpu_backends/transform_reduce.h
M libcxx/include/__algorithm/pstl_copy.h
M libcxx/include/__algorithm/pstl_count.h
M libcxx/include/__algorithm/pstl_equal.h
M libcxx/include/__algorithm/pstl_fill.h
M libcxx/include/__algorithm/pstl_find.h
M libcxx/include/__algorithm/pstl_for_each.h
M libcxx/include/__algorithm/pstl_generate.h
M libcxx/include/__algorithm/pstl_is_partitioned.h
M libcxx/include/__algorithm/pstl_merge.h
M libcxx/include/__algorithm/pstl_move.h
M libcxx/include/__algorithm/pstl_replace.h
M libcxx/include/__algorithm/pstl_rotate_copy.h
M libcxx/include/__algorithm/pstl_sort.h
M libcxx/include/__algorithm/pstl_stable_sort.h
M libcxx/include/__algorithm/pstl_transform.h
M libcxx/include/__chrono/convert_to_tm.h
M libcxx/include/__chrono/formatter.h
M libcxx/include/__chrono/ostream.h
M libcxx/include/__chrono/sys_info.h
M libcxx/include/__config_site.in
M libcxx/include/__iterator/cpp17_iterator_concepts.h
M libcxx/include/__numeric/pstl_reduce.h
M libcxx/include/__numeric/pstl_transform_reduce.h
A libcxx/include/__pstl/backends/libdispatch.h
A libcxx/include/__pstl/backends/serial.h
A libcxx/include/__pstl/backends/std_thread.h
A libcxx/include/__pstl/configuration.h
A libcxx/include/__pstl/configuration_fwd.h
M libcxx/include/chrono
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap
M libcxx/src/CMakeLists.txt
M libcxx/src/pstl/libdispatch.cpp
M libcxx/test/libcxx/algorithms/cpp17_iterator_concepts.verify.cpp
A libcxx/test/libcxx/algorithms/pstl.iterator-requirements.verify.cpp
M libcxx/test/libcxx/algorithms/pstl.libdispatch.chunk_partitions.pass.cpp
A libcxx/test/libcxx/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
M libcxx/test/libcxx/vendor/apple/system-install-properties.sh.cpp
M libcxx/test/std/time/time.cal/time.cal.ymd/time.cal.ymd.nonmembers/ostream.pass.cpp
M libcxx/test/std/time/time.clock/time.clock.system/sys_date.ostream.pass.cpp
A libcxx/test/std/time/time.syn/formatter.sys_info.pass.cpp
M libcxx/test/std/time/time.syn/formatter.year_month_day.pass.cpp
A libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/ostream.pass.cpp
M libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp
M libcxx/test/support/test_iterators.h
M libcxx/test/support/test_macros.h
M libcxx/utils/libcxx/test/features.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/source/Expression/IRExecutionUnit.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
A lldb/test/API/commands/process/detach-resumes/Makefile
A lldb/test/API/commands/process/detach-resumes/TestDetachResumes.py
A lldb/test/API/commands/process/detach-resumes/main.cpp
M lldb/test/API/functionalities/breakpoint/breakpoint_command/TestBreakpointCommand.py
M lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/TestingGuide.rst
M llvm/include/llvm/Analysis/SimplifyQuery.h
M llvm/include/llvm/CodeGen/LivePhysRegs.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/RegisterPressure.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/PowerPC/P10InstrResources.td
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCMacroFusion.def
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVScheduleV.td
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
M llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-load.ll
M llvm/test/Analysis/CostModel/X86/bitreverse-codesize.ll
M llvm/test/Analysis/CostModel/X86/bitreverse-latency.ll
M llvm/test/Analysis/CostModel/X86/bitreverse-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/bitreverse.ll
M llvm/test/Analysis/CostModel/X86/fshl-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshl-latency.ll
M llvm/test/Analysis/CostModel/X86/fshl-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshl.ll
M llvm/test/Analysis/CostModel/X86/fshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/fshr-latency.ll
M llvm/test/Analysis/CostModel/X86/fshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/fshr.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-ashr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-lshr-sizelatency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-codesize.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-latency.ll
M llvm/test/Analysis/CostModel/X86/vshift-shl-sizelatency.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
A llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
M llvm/test/CodeGen/AArch64/aarch64-smull.ll
M llvm/test/CodeGen/AArch64/active_lane_mask.ll
M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/AArch64/extbinopload.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
M llvm/test/CodeGen/AArch64/icmp.ll
M llvm/test/CodeGen/AArch64/insert-extend.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/itofp.ll
M llvm/test/CodeGen/AArch64/ldexp.ll
M llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll
M llvm/test/CodeGen/AArch64/llrint-conv.ll
M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
M llvm/test/CodeGen/AArch64/load-insert-zero.ll
M llvm/test/CodeGen/AArch64/logic-shift.ll
M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
M llvm/test/CodeGen/AArch64/neon-extadd.ll
M llvm/test/CodeGen/AArch64/neon-shift-neg.ll
M llvm/test/CodeGen/AArch64/predicated-add-sub.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
M llvm/test/CodeGen/AArch64/reassocmls.ll
M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
M llvm/test/CodeGen/AArch64/sat-add.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
M llvm/test/CodeGen/AArch64/split-vector-insert.ll
M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
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M llvm/test/CodeGen/AArch64/sve-bitcast.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
M llvm/test/CodeGen/AArch64/sve-expand-div.ll
M llvm/test/CodeGen/AArch64/sve-extract-element.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
M llvm/test/CodeGen/AArch64/sve-fcmp.ll
M llvm/test/CodeGen/AArch64/sve-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fcvt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
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M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
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M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
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M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
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M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
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M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
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M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
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M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
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M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
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M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
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M llvm/test/CodeGen/AArch64/sve-split-store.ll
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M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
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M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
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M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
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M llvm/test/CodeGen/RISCV/attributes.ll
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M llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll
M llvm/test/Transforms/InstCombine/hoist-negation-out-of-bias-calculation.ll
M llvm/test/Transforms/InstCombine/hoist-not-from-ashr-operand.ll
M llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll
M llvm/test/Transforms/InstCombine/icmp.ll
M llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
M llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-vector.ll
M llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/masked-merge-add.ll
M llvm/test/Transforms/InstCombine/masked-merge-or.ll
M llvm/test/Transforms/InstCombine/masked-merge-xor.ll
M llvm/test/Transforms/InstCombine/min-positive.ll
M llvm/test/Transforms/InstCombine/minmax-fold.ll
M llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
M llvm/test/Transforms/InstCombine/mul-inseltpoison.ll
M llvm/test/Transforms/InstCombine/mul.ll
M llvm/test/Transforms/InstCombine/not-add.ll
M llvm/test/Transforms/InstCombine/not.ll
M llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
M llvm/test/Transforms/InstCombine/operand-complexity.ll
M llvm/test/Transforms/InstCombine/or.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll
M llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll
M llvm/test/Transforms/InstCombine/pr53357.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-b.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-c.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-d.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
M llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
M llvm/test/Transforms/InstCombine/reuse-constant-from-select-in-icmp.ll
M llvm/test/Transforms/InstCombine/rotate.ll
M llvm/test/Transforms/InstCombine/saturating-add-sub.ll
M llvm/test/Transforms/InstCombine/select-of-bittest.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/select_meta.ll
M llvm/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll
M llvm/test/Transforms/InstCombine/sext.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-lshr.ll
M llvm/test/Transforms/InstCombine/shift-amount-reassociation.ll
M llvm/test/Transforms/InstCombine/shift-logic.ll
M llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll
M llvm/test/Transforms/InstCombine/signmask-of-sext-vs-of-shl-of-zext.ll
M llvm/test/Transforms/InstCombine/sub-not.ll
M llvm/test/Transforms/InstCombine/sub-xor.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
M llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll
M llvm/test/Transforms/InstCombine/trunc.ll
M llvm/test/Transforms/InstCombine/unsigned-mul-lack-of-overflow-check-via-udiv-of-allones.ll
M llvm/test/Transforms/InstCombine/unsigned-mul-overflow-check-via-udiv-of-allones.ll
M llvm/test/Transforms/InstCombine/variable-signext-of-variable-high-bit-extraction.ll
M llvm/test/Transforms/InstCombine/vec_sext.ll
M llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vector-casts.ll
M llvm/test/Transforms/InstCombine/vector-urem.ll
M llvm/test/Transforms/InstCombine/vector-xor.ll
M llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
M llvm/test/Transforms/InstSimplify/AndOrXor.ll
M llvm/test/Transforms/InstSimplify/call.ll
M llvm/test/Transforms/InstSimplify/compare.ll
M llvm/test/Transforms/InstSimplify/constantfold-add-nuw-allones-to-allones.ll
M llvm/test/Transforms/InstSimplify/constantfold-shl-nuw-C-to-C.ll
M llvm/test/Transforms/InstSimplify/div.ll
M llvm/test/Transforms/InstSimplify/fast-math-strictfp.ll
M llvm/test/Transforms/InstSimplify/fast-math.ll
M llvm/test/Transforms/InstSimplify/fdiv.ll
M llvm/test/Transforms/InstSimplify/floating-point-arithmetic-strictfp.ll
M llvm/test/Transforms/InstSimplify/floating-point-arithmetic.ll
M llvm/test/Transforms/InstSimplify/floating-point-compare.ll
M llvm/test/Transforms/InstSimplify/fminmax-folds.ll
M llvm/test/Transforms/InstSimplify/fp-nan.ll
M llvm/test/Transforms/InstSimplify/icmp-bool-constant.ll
M llvm/test/Transforms/InstSimplify/icmp-not-bool-constant.ll
M llvm/test/Transforms/InstSimplify/ldexp.ll
M llvm/test/Transforms/InstSimplify/mul.ll
M llvm/test/Transforms/InstSimplify/negate.ll
M llvm/test/Transforms/InstSimplify/or.ll
M llvm/test/Transforms/InstSimplify/ptrmask.ll
M llvm/test/Transforms/InstSimplify/rem.ll
M llvm/test/Transforms/InstSimplify/saturating-add-sub.ll
M llvm/test/Transforms/InstSimplify/sdiv.ll
M llvm/test/Transforms/InstSimplify/select-inseltpoison.ll
M llvm/test/Transforms/InstSimplify/select.ll
M llvm/test/Transforms/InstSimplify/shift.ll
M llvm/test/Transforms/InstSimplify/srem.ll
M llvm/test/Transforms/InstSimplify/sub.ll
M llvm/test/Transforms/InstSimplify/xor.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
A llvm/test/Transforms/PhaseOrdering/X86/pr88239.ll
M llvm/test/Transforms/Reassociate/inverses.ll
M llvm/test/Transforms/Reassociate/negation.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/nvptx-basic.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_body/Inputs/basic.test.expected
M llvm/test/tools/UpdateTestChecks/update_test_body/basic.test
M llvm/test/tools/UpdateTestChecks/update_test_body/gen-fail.test
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/stable_ir_values_funcs.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected
A llvm/test/tools/UpdateTestChecks/update_test_checks/various_ir_values_dbgrecords.test
M llvm/test/tools/llvm-dwarfdump/X86/formclass4.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/ConstantsTest.cpp
M llvm/unittests/IR/PatternMatch.cpp
M llvm/unittests/Support/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/UpdateTestChecks/common.py
M llvm/utils/gn/secondary/compiler-rt/lib/sanitizer_common/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/update_test_body.py
M mlir/include/mlir-c/Dialect/NVGPU.h
M mlir/include/mlir-c/Dialect/Transform/Interpreter.h
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Bindings/Python/PybindAdaptors.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
M mlir/include/mlir/IR/CommonAttrConstraints.td
M mlir/include/mlir/Interfaces/ViewLikeInterface.td
A mlir/lib/Bindings/Python/DialectNVGPU.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/TransformInterpreter.cpp
M mlir/lib/CAPI/Dialect/NVGPU.cpp
M mlir/lib/CAPI/Dialect/TransformInterpreter.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparsificationAndBufferizationPass.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/python/CMakeLists.txt
M mlir/python/mlir/dialects/nvgpu.py
M mlir/python/mlir/dialects/transform/interpreter/__init__.py
M mlir/test/CAPI/ir.c
M mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-resize.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/Transform/test-pattern-application.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/python/dialects/nvgpu.py
M mlir/test/python/dialects/transform_interpreter.py
M mlir/test/python/ir/operation.py
M openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
add --shell for debugging. set euo pipefail
Created using spr 1.3.5-bogner
Compare: https://github.com/llvm/llvm-project/compare/105063b29c4e...b9c98dcc042e
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