[all-commits] [llvm/llvm-project] cc82f1: [AArch64] Update latencies for Cortex-A510 schedul...

Wed Apr 17 11:43:14 PDT 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cc82f1290a1e2157a6c0530d78d8cc84d2b8553d
      https://github.com/llvm/llvm-project/commit/cc82f1290a1e2157a6c0530d78d8cc84d2b8553d
  Author: Usman Nadeem <mnadeem at quicinc.com>
  Date:   2024-04-17 (Wed, 17 Apr 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
    M llvm/test/CodeGen/AArch64/aarch64-smull.ll
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
    M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll
    M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
    M llvm/test/CodeGen/AArch64/dag-combine-concat-vectors.ll
    M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/AArch64/extbinopload.ll
    M llvm/test/CodeGen/AArch64/fcmp.ll
    M llvm/test/CodeGen/AArch64/fdiv-combine.ll
    M llvm/test/CodeGen/AArch64/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AArch64/fp-veclib-expansion.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
    M llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/AArch64/icmp.ll
    M llvm/test/CodeGen/AArch64/insert-extend.ll
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/ldexp.ll
    M llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
    M llvm/test/CodeGen/AArch64/load-insert-zero.ll
    M llvm/test/CodeGen/AArch64/logic-shift.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/neon-extadd.ll
    M llvm/test/CodeGen/AArch64/neon-shift-neg.ll
    M llvm/test/CodeGen/AArch64/predicated-add-sub.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AArch64/rcpc3-sve.ll
    M llvm/test/CodeGen/AArch64/reassocmls.ll
    M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
    M llvm/test/CodeGen/AArch64/sat-add.ll
    M llvm/test/CodeGen/AArch64/sext.ll
    M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
    M llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll
    M llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll
    M llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll
    M llvm/test/CodeGen/AArch64/split-vector-insert.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
    M llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
    M llvm/test/CodeGen/AArch64/sve-abd.ll
    M llvm/test/CodeGen/AArch64/sve-bitcast.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
    M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll
    M llvm/test/CodeGen/AArch64/sve-doublereduct.ll
    M llvm/test/CodeGen/AArch64/sve-expand-div.ll
    M llvm/test/CodeGen/AArch64/sve-extract-element.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-from-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fcmp.ll
    M llvm/test/CodeGen/AArch64/sve-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve-fcvt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-addressing-modes.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-mask-opt.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-128bit-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle-tbl.ll
    M llvm/test/CodeGen/AArch64/sve-fp-int-min-max.ll
    M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
    M llvm/test/CodeGen/AArch64/sve-fp-reduce-fadda.ll
    M llvm/test/CodeGen/AArch64/sve-fptosi-sat.ll
    M llvm/test/CodeGen/AArch64/sve-fptoui-sat.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
    M llvm/test/CodeGen/AArch64/sve-hadd.ll
    M llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
    M llvm/test/CodeGen/AArch64/sve-insert-element.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.ll
    M llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
    M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-pr62151.ll
    M llvm/test/CodeGen/AArch64/sve-pred-arith.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
    M llvm/test/CodeGen/AArch64/sve-pred-selectop3.ll
    M llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
    M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
    M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
    M llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-split-load.ll
    M llvm/test/CodeGen/AArch64/sve-split-store.ll
    M llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-stepvector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
    M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-dot.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
    M llvm/test/CodeGen/AArch64/sve2-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve2-fixed-length-fcopysign.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-combine-rshrnb.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-arith-imm.ll
    M llvm/test/CodeGen/AArch64/sve2-rsh.ll
    M llvm/test/CodeGen/AArch64/sve2-xar.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx2.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
    M llvm/test/CodeGen/AArch64/vec_uaddo.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll
    M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
    M llvm/test/CodeGen/AArch64/vector-gep.ll
    M llvm/test/CodeGen/AArch64/vselect-constants.ll
    M llvm/test/CodeGen/AArch64/zext-to-tbl.ll
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s

  Log Message:
  -----------
  [AArch64] Update latencies for Cortex-A510 scheduling model (#87293)

Updated according to the Software Optimization Guide for Arm®
Cortex®‑A510 Core Revision: r1p3 Issue 6.0.

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