[all-commits] [llvm/llvm-project] 5e37ee: [MLIR][Mem2Reg][LLVM] Enhance partial load support

[Christian Ulmann via All-commits]

  Branch: refs/heads/users/dinistro/mem2reg-allow-smaller-accesses
  Home:   https://github.com/llvm/llvm-project
  Commit: 5e37eebaa3df3be5f6569320e2dcbcbfde2b4102
      https://github.com/llvm/llvm-project/commit/5e37eebaa3df3be5f6569320e2dcbcbfde2b4102
  Author: Christian Ulmann <christian.ulmann at nextsilicon.com>
  Date:   2024-04-17 (Wed, 17 Apr 2024)

  Changed paths:
    M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
    M mlir/lib/Transforms/Mem2Reg.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [MLIR][Mem2Reg][LLVM] Enhance partial load support

This commit improves LLVM dialect's Mem2Reg interfaces to support
promotions of partial loads from larger memory slots. To support this,
the Mem2Reg interface methods are extended with additional data layout
parameters. The data layout is required to determine type sizes to
produce correct conversion sequences.



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