[all-commits] [llvm/llvm-project] d19bd0: Clang Release Notes: Fix reST formatting

Tue Apr 16 16:10:50 PDT 2024

  Branch: refs/heads/users/darkbuck/spr/sparc-fix-instr-desc-of-special-register-stores
  Home:   https://github.com/llvm/llvm-project
  Commit: d19bd05c79ad3b1a2c3cb439c3fc60825f66bed7
      https://github.com/llvm/llvm-project/commit/d19bd05c79ad3b1a2c3cb439c3fc60825f66bed7
  Author: Hubert Tong <hubert-reinterpretcast at users.noreply.github.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst

  Log Message:
  -----------
  Clang Release Notes: Fix reST formatting

Fix a use of inline code markup to have a non-word character after the ending delimiter as required by reST.

  Commit: 3074060d6a1d7d2e74cb767876bd9e5192d12007
      https://github.com/llvm/llvm-project/commit/3074060d6a1d7d2e74cb767876bd9e5192d12007
  Author: Kazu Hirata <kazu at google.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M llvm/unittests/ProfileData/MemProfTest.cpp

  Log Message:
  -----------
  [memprof] Use SizeIs (NFC) (#88984)

  Commit: b1385dbd98e877a374ce303fd9d1774faf98e31b
      https://github.com/llvm/llvm-project/commit/b1385dbd98e877a374ce303fd9d1774faf98e31b
  Author: Michael Jones <michaelrj at google.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M libc/hdr/types/CMakeLists.txt

  Log Message:
  -----------
  [libc][NFC] fix typo in fenv type proxy headers (#88982)

libc.incude.fenv ->
libc.include.fenv

  Commit: 8aa061ffc75adfab4b3084c918e7d4a3ccd5ba43
      https://github.com/llvm/llvm-project/commit/8aa061ffc75adfab4b3084c918e7d4a3ccd5ba43
  Author: Peiming Liu <peiming at google.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td

  Log Message:
  -----------
  [mlir][sparse][NFC] switching to using `let argments/results` in td files (#88994)

followed the same style used in "TensorOps.td".

  Commit: 9067070d91e9d8cdd8509ffa56a076f08a3d7281
      https://github.com/llvm/llvm-project/commit/9067070d91e9d8cdd8509ffa56a076f08a3d7281
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-features.c
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/pr56110.ll
    M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
    M llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)

This is largely a revert of commit
e81796671890b59c110f8e41adc7ca26f8484d20.

As #88029 shows, there exists hardware that only supports unaligned
scalar.

I'm leaving how this gets exposed to the clang interface to a future
patch.

  Commit: 988ffd06722e7e056b239efe497345ac97be33db
      https://github.com/llvm/llvm-project/commit/988ffd06722e7e056b239efe497345ac97be33db
  Author: Usama Hameed <u_hameed at apple.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M lldb/test/API/functionalities/asan/Makefile
    M lldb/test/API/functionalities/asan/TestMemoryHistory.py
    M lldb/test/API/functionalities/asan/TestReportData.py

  Log Message:
  -----------
  Add asan tests for libsanitizers. (#88349) (#88962)

The previous patch was reverted because the test fails to build when
libsanitizers is not present. This patch catches the BuildError
exception and skips the test appropriately.

This patch tests LLDB integration with libsanitizers for ASan.

rdar://111856681

  Commit: 50a371795bcfe0731f8882e42712dff33cbbef9b
      https://github.com/llvm/llvm-project/commit/50a371795bcfe0731f8882e42712dff33cbbef9b
  Author: darkbuck <michael.hliao at gmail.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrCMovSetCC.td

  Log Message:
  -----------
  [X86] Fix instr desc of CFCMOV's 'mr' variants

- With the memory operand as the destination, 'mr' variants of CFCMOV
  works like STORE and their memory operands should be input operands
  instead of output ones.

Reviewers: XinWang10, arsenm

Pull Request: https://github.com/llvm/llvm-project/pull/88970

  Commit: 87213e1c5824b6992ec1e54ce740338c2642d137
      https://github.com/llvm/llvm-project/commit/87213e1c5824b6992ec1e54ce740338c2642d137
  Author: Michael Liao <michael.hliao at gmail.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-features.c
    M libc/hdr/types/CMakeLists.txt
    M lldb/test/API/functionalities/asan/Makefile
    M lldb/test/API/functionalities/asan/TestMemoryHistory.py
    M lldb/test/API/functionalities/asan/TestReportData.py
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/pr56110.ll
    M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
    M llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/unittests/ProfileData/MemProfTest.cpp
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
    M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td

  Log Message:
  -----------
  [𝘀𝗽𝗿] landed version

Created using spr 1.3.4

Compare: https://github.com/llvm/llvm-project/compare/1ba93de384a8...87213e1c5824

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