[all-commits] [llvm/llvm-project] 906707: [RISCV] Re-separate unaligned scalar and vector me...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9067070d91e9d8cdd8509ffa56a076f08a3d7281
      https://github.com/llvm/llvm-project/commit/9067070d91e9d8cdd8509ffa56a076f08a3d7281
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/Driver/riscv-features.c
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/memcpy.ll
    M llvm/test/CodeGen/RISCV/memset-inline.ll
    M llvm/test/CodeGen/RISCV/pr56110.ll
    M llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
    M llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll
    M llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

  Log Message:
  -----------
  [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)

This is largely a revert of commit
e81796671890b59c110f8e41adc7ca26f8484d20.

As #88029 shows, there exists hardware that only supports unaligned
scalar.

I'm leaving how this gets exposed to the clang interface to a future
patch.



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