[all-commits] [llvm/llvm-project] dbaa18: [RISCV] Generate more W instructons

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbaa1893c9afe6a245860efb8d68875ba4fd6794
      https://github.com/llvm/llvm-project/commit/dbaa1893c9afe6a245860efb8d68875ba4fd6794
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    A llvm/test/CodeGen/RISCV/prefer-w-inst.ll
    A llvm/test/CodeGen/RISCV/prefer-w-inst.mir
    R llvm/test/CodeGen/RISCV/strip-w-suffix.ll

  Log Message:
  -----------
  [RISCV] Generate more W instructons

We rename `TuneNoStripWSuffix` to `TunePreferWInst`.

If all the users of an instruction just use the low 32 bits, we can
convert it to its W variant.

A quick test on Coremark (`-O3 -march=rv64gc`):

|        | W instructions | code size(.text) |
|--------|----------------|------------------|
| before | 302            | 12257            |
| after  | 343            | 12265            |
|        | +13.58%        | +0.065%          |

Reviewers: asb, dtcxzyw, preames, lukel97, michaelmaitland, topperc

Reviewed By: topperc, dtcxzyw

Pull Request: https://github.com/llvm/llvm-project/pull/87237



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