[all-commits] [llvm/llvm-project] 6da196: [RISCV] Add scheduling information for SiFive VCIX...

[Michal Terepeta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6da1966bc503e1ce44ef36e7107c9db482fac6ab
      https://github.com/llvm/llvm-project/commit/6da1966bc503e1ce44ef36e7107c9db482fac6ab
  Author: Michal Terepeta <michalt at google.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
    M llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
    M llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td
    A llvm/lib/Target/RISCV/RISCVScheduleXSf.td

  Log Message:
  -----------
  [RISCV] Add scheduling information for SiFive VCIX (#86093)

This adds `RISCVScheduleXSf.td` with `SchedWrite` definitions for all
VCIX instructions and uses it in `RISCVSchedSiFive7.td` to set default
latencies for these instructions, helping with issue
https://github.com/llvm/llvm-project/issues/83391. Of course these
default latencies cannot be accurate (since each coprocessor will have
different latencies), but this seems to be enough to avoid some of the
problematic behavior described in the bug.

In any case, this seems to be enough to help with #83391 in our internal
testing.

A subsequent discussion is how to structure the code such that it's
easier for downstream consumers of this to use `SiFive7` scheduling
model with accurate VCIX latencies. But we can probably have a separate
issue to discuss that.



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