[all-commits] [llvm/llvm-project] eaae76: [RISCV] Support rv{32, 64}e in the compiler builti...

[Cyrill Leutwiler via All-commits]

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: eaae766a20fdd2d5f0c6b3f04d7f238a6aa1f814
      https://github.com/llvm/llvm-project/commit/eaae766a20fdd2d5f0c6b3f04d7f238a6aa1f814
  Author: Cyrill Leutwiler <bigcyrill at hotmail.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M compiler-rt/lib/builtins/riscv/restore.S
    M compiler-rt/lib/builtins/riscv/save.S

  Log Message:
  -----------
  [RISCV] Support rv{32, 64}e in the compiler builtins (#88252)

Register spills (save/restore) in RISC-V embedded work differently
because there are less registers and different stack alignment.

[GCC equivalent
](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336)

Follow up from #76777.

---------

Signed-off-by: xermicus <cyrill at parity.io>
(cherry picked from commit bd32aaa8c9ec2094f605315b3989adc2a567ca98)



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