[all-commits] [llvm/llvm-project] b5b17b: [RISCV] Fix assertion failure in `genShXAddAddShif...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5b17bf613010b5ea900d2981365b9d2c846a20f
      https://github.com/llvm/llvm-project/commit/b5b17bf613010b5ea900d2981365b9d2c846a20f
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-04-16 (Tue, 16 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Fix assertion failure in `genShXAddAddShift` (#88757)

Fix assertion failure in our downstream CI
https://github.com/dtcxzyw/llvm-codegen-benchmark/issues/1.



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