[all-commits] [llvm/llvm-project] 9dbb6e: [mlir][spirv] Add target width to SPIR-V ABI (#88555)

[Hsiangkai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9dbb6e1978d3d2d61ef65c2dac1fd8add5a4c7a2
      https://github.com/llvm/llvm-project/commit/9dbb6e1978d3d2d61ef65c2dac1fd8add5a4c7a2
  Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
  Date:   2024-04-15 (Mon, 15 Apr 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAttributes.td
    M mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
    M mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
    M mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
    M mlir/test/Conversion/GPUToSPIRV/entry-point.mlir
    M mlir/test/lib/Dialect/SPIRV/TestEntryPointAbi.cpp

  Log Message:
  -----------
  [mlir][spirv] Add target width to SPIR-V ABI (#88555)

There are execution modes need target width as their extra operands.
SignedZeroInfNanPreserve is one of them. This patch adds `target width`
as one of SPIR-V ABI attributes.



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