[all-commits] [llvm/llvm-project] 73ddb2: [RISCV] Store VLMul/NF into RegisterClass's TSFlags

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73ddb2a7471986a7ed600dbea14efc60f0d0db47
      https://github.com/llvm/llvm-project/commit/73ddb2a7471986a7ed600dbea14efc60f0d0db47
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-08 (Mon, 08 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Store VLMul/NF into RegisterClass's TSFlags

This TSFlags was introduced by https://reviews.llvm.org/D108767.

A base class of all RISCV RegisterClass is added and we store
IsVRegClass/VLMul/NF into TSFlags and add helpers to get them.

This can reduce some lines and I think there will be more usages.

Reviewers: preames, topperc

Reviewed By: topperc

Pull Request: https://github.com/llvm/llvm-project/pull/84894



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