[all-commits] [llvm/llvm-project] f3b559: [RISCV] Use larger copies when register tuples are...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/users/wangpc-pp/spr/riscv-store-vlmulnf-into-registerclasss-tsflags
  Home:   https://github.com/llvm/llvm-project
  Commit: f3b55973645d551d67af7662b815a5f415874ff7
      https://github.com/llvm/llvm-project/commit/f3b55973645d551d67af7662b815a5f415874ff7
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-08 (Mon, 08 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir

  Log Message:
  -----------
  [RISCV] Use larger copies when register tuples are aligned

When the encoding of register tuples are aligned, we can use a copy
with larger LMUL to reduce copies.

Reviewers: preames, topperc, lukel97

Reviewed By: topperc, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/84455


  Commit: e32cc2627d3798cb19f27675e73cef92c17527d4
      https://github.com/llvm/llvm-project/commit/e32cc2627d3798cb19f27675e73cef92c17527d4
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-08 (Mon, 08 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]


  Commit: e4482ce94107bd7a75146f5b98f227608f1222db
      https://github.com/llvm/llvm-project/commit/e4482ce94107bd7a75146f5b98f227608f1222db
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-04-08 (Mon, 08 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  Rebase

Created using spr 1.3.6-beta.1


Compare: https://github.com/llvm/llvm-project/compare/53665b1ae642...e4482ce94107

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