[all-commits] [llvm/llvm-project] 974f1e: [MLIR][LLVM][Mem2Reg] Relax type equality requirem...

[Christian Ulmann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 974f1ee58da1c51c547eaf5c7007a215fd286c68
      https://github.com/llvm/llvm-project/commit/974f1ee58da1c51c547eaf5c7007a215fd286c68
  Author: Christian Ulmann <christianulmann at gmail.com>
  Date:   2024-04-05 (Fri, 05 Apr 2024)

  Changed paths:
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [MLIR][LLVM][Mem2Reg] Relax type equality requirement for load and store (#87637)

This commit relaxes Mem2Reg's type equality requirement for the LLVM
dialect's load and store operations. For now, we only allow loads to be
promoted if the reaching definition can be casted into a value of the
target type.

For stores, the same conversion casting check is applied and we ensure
that their result is properly casted to the type of the memory slot.
This is necessary to satisfy assumptions of the general mem2reg pass, as
it creates block arguments with the types of the memory slot.

This relands https://github.com/llvm/llvm-project/pull/87504



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