[all-commits] [llvm/llvm-project] 852eb2: [RISCV][GISel] Make register bank selection for un...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 852eb20b4f091a535ef758407d8555798b0ad809
      https://github.com/llvm/llvm-project/commit/852eb20b4f091a535ef758407d8555798b0ad809
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-04-04 (Thu, 04 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

  Log Message:
  -----------
  [RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. (#87593)

This is inspired by AArch64's getSameKindOfOperandsMapping, but based on
what RISC-V currently needs.

This removes the special vector case for G_ADD/SUB and unifies integer
and FP operations into the same handler.

G_SEXTLOAD/ZEXTLOAD have been separated from integer since they should
only be scalar integer and never vector.



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