[all-commits] [llvm/llvm-project] d6e458: [MLIR][LLVM][Mem2Reg] Relax type equality requirem...

[Christian Ulmann via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d6e458219897fad0e460e663833b2190af48c06d
      https://github.com/llvm/llvm-project/commit/d6e458219897fad0e460e663833b2190af48c06d
  Author: Christian Ulmann <christianulmann at gmail.com>
  Date:   2024-04-04 (Thu, 04 Apr 2024)

  Changed paths:
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [MLIR][LLVM][Mem2Reg] Relax type equality requirement for load and store (#87504)

This commit relaxes Mem2Reg's type equality requirement for the LLVM
dialect's load and store operations. For now, we only allow loads to be
promoted if the reaching definition can be casted into a value of the
target type.

For stores, all type checks are removed, as a non-volatile store that
does not write out the alloca's pointer can always be deleted.



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