[all-commits] [llvm/llvm-project] 07d5f4: [RISCV] Add patterns for fixed vector vwsll (#87316)

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 07d5f491867d390b9aee33035c187e27cf0746a0
      https://github.com/llvm/llvm-project/commit/07d5f491867d390b9aee33035c187e27cf0746a0
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-04-04 (Thu, 04 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll

  Log Message:
  -----------
  [RISCV] Add patterns for fixed vector vwsll (#87316)

Fixed vectors have their sext/zext operands legalized to _VL nodes, so
we need to handle them in the patterns.

This adds a riscv_ext_vl_oneuse pattern since we don't care about the
type of extension used for the shift amount, and extends
Low8BitsSplatPat to handle other _VL nodes. We don't actually need to
check the mask or VL there since none of the _VL nodes have passthru
operands.

The remaining test cases that are widening from i8->i64 need to be
handled by extending combineBinOp_VLToVWBinOp_VL.

This also fixes Low8BitsSplatPat incorrectly checking the vector size
instead of the element size to determine if the splat value might have
been truncated below 8 bits.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications