[all-commits] [llvm/llvm-project] fff269: [C23] Remove WG14 N2416 from the C status page
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Wed Apr 3 16:22:35 PDT 2024
Branch: refs/heads/users/vitalybuka/spr/clangcodegen-guard-ubsan-checks-with-llvmallowubsancheck
Home: https://github.com/llvm/llvm-project
Commit: fff2690eba58f3a548865b5246b09233663c680d
https://github.com/llvm/llvm-project/commit/fff2690eba58f3a548865b5246b09233663c680d
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
[C23] Remove WG14 N2416 from the C status page
This paper did not add any normative changes for us to check
conformance against. It added a note describing a potential behavioral
difference between compile-time and runtime evaluation of negative
floating-point values in the presence of rounding modes.
Commit: 07d3f2a8de6956717db2355d6d3421d35f3a5796
https://github.com/llvm/llvm-project/commit/07d3f2a8de6956717db2355d6d3421d35f3a5796
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir
Log Message:
-----------
[RISCV][GISEL] Run update_mir_test_checks on llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir
Commit: 23616c65e7d632e750ddb67d55cc39098a69a8a6
https://github.com/llvm/llvm-project/commit/23616c65e7d632e750ddb67d55cc39098a69a8a6
Author: maflcko <6399679+maflcko at users.noreply.github.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/tools/dsymutil/CMakeLists.txt
Log Message:
-----------
dsymutil: Re-add missing -latomic (#85380)
This was accidentally removed in
https://reviews.llvm.org/D137799#4657404 /
https://reviews.llvm.org/D137799#C3933303OL44, and downstream projects
are forced to add it back. For example,
https://git.savannah.gnu.org/cgit/guix.git/commit/?id=4e26331a5ee87928a16888c36d51e270f0f10f90
Fix this, by re-adding it.
Co-authored-by: MarcoFalke <*~=`'#}+{/-|&$^_ at 721217.xyz>
Commit: cd29126b6333c28cc4df7b932ed0d6d6c13983d1
https://github.com/llvm/llvm-project/commit/cd29126b6333c28cc4df7b932ed0d6d6c13983d1
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
Log Message:
-----------
[SLP]Fix PR87133: crash because of different altopcodes for cmps after reordering.
If the node has cmp instruction with 3 or more different but swappable
predicates, need to keep same kind of main/alternate opcodes to avoid
incorrect detection of opcodes after reordering. Reordering changes the
order and we may erroneously consider swappable opcodes as
non-compatible/alternate, which may lead to a later compiler crash.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/87267
Commit: fbcd0c65f7b2f65e0ee58e5448b88af39faf10f1
https://github.com/llvm/llvm-project/commit/fbcd0c65f7b2f65e0ee58e5448b88af39faf10f1
Author: Rafael Ubal <rubal at mathworks.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
Updates to 'tosa.reshape' verifier (#87416)
This addition catches common cases of malformed `tosa.reshape` ops. This
prevents the `--tosa-to-tensor` pass from asserting when fed invalid
operations, as these will be caught ahead of time by the verifier.
Closes #87396
Commit: d83233f597f6d512bf7109bb4c33a7fdd2f8fd31
https://github.com/llvm/llvm-project/commit/d83233f597f6d512bf7109bb4c33a7fdd2f8fd31
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M libcxx/docs/Status/Cxx23.rst
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
Log Message:
-----------
[libc++] Mark some recent LWG issues and papers as done (#87502)
Justifications:
- LWG3950: Done in #66206
- LWG3975: Wording changes only
- LWG4011: Wording changes only
- LWG4030: Wording changes only
- LWG4043: Wording changes only
- LWG3036 and P2875R4: We implemented neither, but the latter reverts
the former, so now we implement both without doing anything!
Commit: d5ec49ff3dc26cdbe350e9cafc6b8e331fff7911
https://github.com/llvm/llvm-project/commit/d5ec49ff3dc26cdbe350e9cafc6b8e331fff7911
Author: Chenguang Wang <w3cing at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M mlir/lib/Support/Timing.cpp
Log Message:
-----------
[mlir] Initialize DefaultTimingManager::out. (#87522)
`DefaultTimingManager::clear()` uses `out` to initialize `TimerImpl`,
but the `out` is `nullptr` by default. This means if
`DefaultTimingManager::setOutput()` is never called,
`DefaultTimingManager` destructor may generate SIGSEGV.
Commit: a94a3cd3d6d4ca6cadaafc29c8097bd2fe078b9d
https://github.com/llvm/llvm-project/commit/a94a3cd3d6d4ca6cadaafc29c8097bd2fe078b9d
Author: Lei Wang <wlei at fb.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
M llvm/test/Transforms/SampleProfile/pseudo-probe-callee-profile-mismatch.ll
Log Message:
-----------
Always check the function attribute to determine checksum mismatch for available_externally functions (#87279)
This is to fix an assertion error. Apparently, `pseudo_probe_desc` could
still be available for import functions, and its checksum mismatch state
can be different from import function's `profile-checksum-mismatch`
attr. This happens when unstable IR or ODR violation issue occurs, the
definitions of the same function across different translation units
could be different and result in different checksums. During link time
deduplication, the internal function definition (the checksum in desc is
computed based on) is substituted by the `available_externally`
definition, which cause the inconsistency. Hence, we fix it to by always
checking the state for the new `available_externally` definition, which
is saved in the function attribute.
Commit: 8a5a1b770413bb62ff27cd8c2aea3d04b3a95bbe
https://github.com/llvm/llvm-project/commit/8a5a1b770413bb62ff27cd8c2aea3d04b3a95bbe
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/UndefinedBehaviorSanitizer.rst
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.h
A clang/test/CodeGen/ubsan-bitfield-conversion.c
A clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp
M clang/test/Driver/fsanitize.c
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers.h
Log Message:
-----------
Revert "Revert "[clang][UBSan] Add implicit conversion check for bitfields"" (#87529)
Reverts llvm/llvm-project#87518
Revert is not needed as the regression was fixed with
1189e87951e59a81ee097eae847c06008276fef1.
I assumed the crash and warning are different issues, but according to
https://lab.llvm.org/buildbot/#/builders/240/builds/26629
fixing warning resolves the crash.
Commit: 42c7bc04c30b427414a2d957776b1655abb27b6e
https://github.com/llvm/llvm-project/commit/42c7bc04c30b427414a2d957776b1655abb27b6e
Author: David Green <david.green at arm.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
A clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
Log Message:
-----------
[AArch64][ARM] Make neon fp16 generic intrinsics always available. (#87467)
By generic intrinsics this mean things like dup, ext, zip and bsl that
can always be executed with integer s16 operations and do not require
fullfp16. This makes them always available, and brings them inline with
GCC.
https://godbolt.org/z/azs8eMv54
The relevant test cases have been moved into their own files, to allow
them to be tested with armv8-a and armv8.2-a+fp16.
Commit: 5bbce06ac642bedcb93158ed04253cf6deedf5e6
https://github.com/llvm/llvm-project/commit/5bbce06ac642bedcb93158ed04253cf6deedf5e6
Author: Lei Wang <wlei at fb.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M clang/test/CodeGen/pseudo-probe-emit.c
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/Transforms/IPO/SampleProfileProbe.h
M llvm/lib/Transforms/IPO/SampleProfileProbe.cpp
M llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile.prof
M llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-update.prof
M llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-discriminator.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-invoke.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-metadata-2.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-update.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-verify.ll
Log Message:
-----------
[PseudoProbe] Mix block and call probe ID in lexical order (#75092)
Before all the call probe ids are after block ids, in this change, it
mixed the call probe and block probe by reordering them in
lexical(line-number) order. For example:
```
main():
BB1
if(...)
BB2 foo(..);
else
BB3 bar(...);
BB4
```
Before the profile is
```
main
1: ..
2: ..
3: ...
4: ...
5: foo ...
6: bar ...
```
Now the new order is
```
main
1: ..
2: ..
3: foo ...
4: ...
5: bar ...
6: ...
```
This can potentially make it more tolerant of profile mismatch, either from stale profile or frontend change. e.g. before if we add one block, even the block is the last one, all the call probes are shifted and mismatched. Moreover, this makes better use of call-anchor based stale profile matching. Blocks are matched based on the closest anchor, there would be more anchors used for the matching, reduce the mismatch scope.
Commit: d57884011e8c57b118b831614b692ba4bc8b5aca
https://github.com/llvm/llvm-project/commit/d57884011e8c57b118b831614b692ba4bc8b5aca
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/slp-umax-rdx-matcher-crash.ll
Log Message:
-----------
[SLP]Add support for commutative intrinsics.
Implemented long-standing TODO to support commutative intrinsics.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/86316
Commit: b15d27e24902444129bfec4095d68bf80f3af700
https://github.com/llvm/llvm-project/commit/b15d27e24902444129bfec4095d68bf80f3af700
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
Log Message:
-----------
[VectorCombine][X86] Add additional tests for #87510
Add zext nneg tests and check we don't fold casts with different src types
Commit: 52ae02db4044b5d6e55b48133ac641b0c998ef49
https://github.com/llvm/llvm-project/commit/52ae02db4044b5d6e55b48133ac641b0c998ef49
Author: David Green <david.green at arm.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
Log Message:
-----------
[AArch64] Add a test for non-temporal masked loads / stores. NFC
Commit: 7c68a958e2213a5190d91ce6dddddb72ce732f1e
https://github.com/llvm/llvm-project/commit/7c68a958e2213a5190d91ce6dddddb72ce732f1e
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/DSDIRInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC (#87537)
We should consistently use PseudoInstr instead of Mnemonic to name
SIMCInstr, even though they may be the same in most cases
Commit: e29228efae67cadfd18c532f944d19b4e16ff229
https://github.com/llvm/llvm-project/commit/e29228efae67cadfd18c532f944d19b4e16ff229
Author: Joe Nash <joseph.nash at amd.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/MC/AMDGPU/gfx1150_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
Log Message:
-----------
[AMDGPU][MC] Allow VOP3C dpp src1 to be imm or SGPR (#87418)
Allows src1 of VOP3 encoded VOPC to be an SGPR or inline immediate on
GFX1150Plus
The w32 and w64 _e64_dpp assembler only real instructions were unused,
and erroneously constructed in a way that bugged parsing of the new
instructions. They are removed.
This patch is a follow up to PR
https://github.com/llvm/llvm-project/pull/87382
Commit: a8425d2fa2e0d29b83d16eac008441ecb9516320
https://github.com/llvm/llvm-project/commit/a8425d2fa2e0d29b83d16eac008441ecb9516320
Author: Kevin Frei <kevinfrei at users.noreply.github.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolLocator/CMakeLists.txt
M lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
A lldb/test/API/debuginfod/Normal/Makefile
A lldb/test/API/debuginfod/Normal/TestDebuginfod.py
A lldb/test/API/debuginfod/Normal/main.c
A lldb/test/API/debuginfod/SplitDWARF/Makefile
A lldb/test/API/debuginfod/SplitDWARF/TestDebuginfodDWP.py
A lldb/test/API/debuginfod/SplitDWARF/main.c
Log Message:
-----------
DebugInfoD issues, take 2 (#86812)
The previous diff (and it's subsequent fix) were reverted as the tests
didn't work properly on the AArch64 & ARM LLDB buildbots. I made a
couple more minor changes to tests (from @clayborg's feedback) and
disabled them for non Linux-x86(_64) builds, as I don't have the ability
do anything about an ARM64 Linux failure. If I had to guess, I'd say the
toolchain on the buildbots isn't respecting the `-Wl,--build-id` flag.
Maybe, one day, when I have a Linux AArch64 system I'll dig in to it.
>From the reverted PR:
I've migrated the tests in my
https://github.com/llvm/llvm-project/pull/79181 from shell to API (at
@JDevlieghere's suggestion) and addressed a couple issues that were
exposed during testing.
The tests first test the "normal" situation (no DebugInfoD involvement,
just normal debug files sitting around), then the "no debug info"
situation (to make sure the test is seeing failure properly), then it
tests to validate that when DebugInfoD returns the symbols, things work
properly. This is duplicated for DWP/split-dwarf scenarios.
---------
Co-authored-by: Kevin Frei <freik at meta.com>
Commit: 607b4bc602eda79e97a91a9bc3552a6004e5ac47
https://github.com/llvm/llvm-project/commit/607b4bc602eda79e97a91a9bc3552a6004e5ac47
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
Log Message:
-----------
[AMDGPU] Add a missing COV6 case to getAMDHSACodeObjectVersion() (#87492)
Commit: 899855d2b11856a44e530fffe854d76be69b9008
https://github.com/llvm/llvm-project/commit/899855d2b11856a44e530fffe854d76be69b9008
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
Log Message:
-----------
[SLP]Improve minbitwidth analysis for operands of IToFP and ICmp instructions.
Compiler can improve analysis for operands of UIToFP/SIToFP instructions
and operands of ICmp instruction.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/85966
Commit: fa2bbea14df3273b3403f34cc295c56233fdbd0d
https://github.com/llvm/llvm-project/commit/fa2bbea14df3273b3403f34cc295c56233fdbd0d
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
Log Message:
-----------
Revert "[SLP]Improve minbitwidth analysis for operands of IToFP and ICmp instructions."
This reverts commit 899855d2b11856a44e530fffe854d76be69b9008 to fix the
issue reported in https://lab.llvm.org/buildbot/#/builders/165/builds/51659.
Commit: e506dd0f14ea9fe0b0ac6c3492a118d4d2244fee
https://github.com/llvm/llvm-project/commit/e506dd0f14ea9fe0b0ac6c3492a118d4d2244fee
Author: Christopher Di Bella <cjdb at google.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/include/llvm/ADT/iterator_range.h
Log Message:
-----------
fully qualifies use of `detail` namespace (#87536)
Some TUs apparently end up with an ambiguity between `::llvm::detail`
and `support::detail`, so we close that gap at the source.
Commit: 3ee93f486293420852fb9ec95af9c5f54cecdb08
https://github.com/llvm/llvm-project/commit/3ee93f486293420852fb9ec95af9c5f54cecdb08
Author: Shourya Goel <shouryagoel10000 at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M libc/config/baremetal/api.td
M libc/config/gpu/api.td
M libc/config/linux/api.td
M libc/include/CMakeLists.txt
M libc/spec/posix.td
M libc/src/stdio/fseeko.h
M libc/src/stdio/ftello.h
Log Message:
-----------
[libc] Added transitive bindings for OffsetType (#87397)
Adding OffTType to fcntl.h and stdio.h 's Macro lists in libc/spec/posix.td as
mentioned here: #87266
Commit: 42cbceb0f0160d67145723613fda325dbd129308
https://github.com/llvm/llvm-project/commit/42cbceb0f0160d67145723613fda325dbd129308
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
Log Message:
-----------
[SLP]Improve minbitwidth analysis for operands of IToFP and ICmp instructions.
Compiler can improve analysis for operands of UIToFP/SIToFP instructions
and operands of ICmp instruction.
Reviewers: RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/85966
Commit: d53b8291bff4542a9c3e2f1df050deafbe295fff
https://github.com/llvm/llvm-project/commit/d53b8291bff4542a9c3e2f1df050deafbe295fff
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
Log Message:
-----------
[VectorCombine][X86] shuffle-of-casts.ll - adjust zext nneg tests to improve costs for testing
Improves SSE vs AVX test results for #87510
Commit: 718638d44d3f1033c1ea395244c07d971ec33a90
https://github.com/llvm/llvm-project/commit/718638d44d3f1033c1ea395244c07d971ec33a90
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M flang/include/flang/Runtime/io-api.h
M flang/runtime/environment.cpp
M flang/runtime/environment.h
M flang/runtime/freestanding-tools.h
M flang/runtime/io-api.cpp
M flang/runtime/io-error.cpp
M flang/runtime/io-error.h
M flang/runtime/namelist.cpp
Log Message:
-----------
[flang][runtime] Enable I/O APIs in F18 runtime offload builds. (#87543)
Commit: 4078763e2e73b4ef3f9e728f66cdf9e429d3f7a4
https://github.com/llvm/llvm-project/commit/4078763e2e73b4ef3f9e728f66cdf9e429d3f7a4
Author: Damien L-G <dalg24+github at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
Log Message:
-----------
[libc++] Fix copy/pasta error in atomic tests for `atomic_compare_exchange_{weak,strong}` (#87135)
Spotted this minor mistake in the tests as I was looking into testing
more thoroughly `atomic_ref`.
The two argument overloads are tested just above. The names of the
lambda clearly indicates that the intent was to test the one argument
overload.
Commit: 029e1d751503268e3d8b01db769e710835c3010d
https://github.com/llvm/llvm-project/commit/029e1d751503268e3d8b01db769e710835c3010d
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/UndefinedBehaviorSanitizer.rst
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.h
R clang/test/CodeGen/ubsan-bitfield-conversion.c
R clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp
M clang/test/Driver/fsanitize.c
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
M compiler-rt/lib/ubsan/ubsan_handlers.h
Log Message:
-----------
Revert "Revert "Revert "[clang][UBSan] Add implicit conversion check for bitfields""" (#87562)
Reverts llvm/llvm-project#87529
Reverts #87518
https://lab.llvm.org/buildbot/#/builders/37/builds/33262 is still broken
Commit: 8aa3a77eaf198afb7e01453e6daf6566b687945d
https://github.com/llvm/llvm-project/commit/8aa3a77eaf198afb7e01453e6daf6566b687945d
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir
M llvm/test/MachineVerifier/test_g_fcmp.mir
M llvm/test/MachineVerifier/test_g_icmp.mir
Log Message:
-----------
[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types
This patch legalizes G_ZEXT, G_SEXT, and G_ANYEXT. If the type is a
legal mask type, then the instruction is legalized as the element-wise
select, where the condition on the select is the mask typed source
operand, and the true and false values are 1 or -1 (for
zero/any-extension and sign extension) and zero. If the type is a legal integer
or vector integer type, then the instruction is marked as legal.
The legalization of the extends may introduce a G_SPLAT_VECTOR, which
needs to be legalized in this patch for the extend test cases to pass.
A G_SPLAT_VECTOR is legal if the vector type is a legal integer or
floating point vector type and the source operand is sXLen type. This is
because the SelectionDAG patterns only support sXLen typed
ISD::SPLAT_VECTORS, and we'd like to reuse those patterns. A
G_SPLAT_VECTOR is cutom legalized if it has a legal s1 element vector
type and s1 scalar operand. It is legalized to G_VMSET_VL or G_VMCLR_VL
if the splat is all ones or all zeros respectivley. In the case of a
non-constant mask splat, we legalize by promoting the scalar value to
s8.
In order to get the s8 element vector back into s1 vector, we use a
G_ICMP. In order for the splat vector and extend tests to pass, we also
need to legalize G_ICMP in this patch.
A G_ICMP is legal if the destination type is a legal bool vector and the LHS and
RHS are legal integer vector types.
Commit: 05f673bcefb0912a38a67b0026cad3768b2f85d2
https://github.com/llvm/llvm-project/commit/05f673bcefb0912a38a67b0026cad3768b2f85d2
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
Log Message:
-----------
[RISCV][GISEL] Regbank select for scalable vector G_ICMP
Commit: 35a9393a3f775d4e1506965b9cfeedd45599f1a7
https://github.com/llvm/llvm-project/commit/35a9393a3f775d4e1506965b9cfeedd45599f1a7
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir
Log Message:
-----------
[RISCV][GISEL] Instruction selection for G_ICMP
Commit: 188ca374ee601a50b6f5f6c1cf7e7dc3998e3a62
https://github.com/llvm/llvm-project/commit/188ca374ee601a50b6f5f6c1cf7e7dc3998e3a62
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
Log Message:
-----------
[RISCV][GISEL] Regbankselect for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type
Commit: 63c925ca808f216f805b76873743450456e350f2
https://github.com/llvm/llvm-project/commit/63c925ca808f216f805b76873743450456e350f2
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
Log Message:
-----------
[RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type
Commit: be57c90feff81d067c83be1ab8927fb345c761cc
https://github.com/llvm/llvm-project/commit/be57c90feff81d067c83be1ab8927fb345c761cc
Author: Gulfem Savrun Yeniceri <gulfem at google.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M llvm/tools/dsymutil/CMakeLists.txt
Log Message:
-----------
Revert "dsymutil: Re-add missing -latomic (#85380)"
This reverts commit 23616c65e7d632e750ddb67d55cc39098a69a8a6
because it breaks Fuchsia Clang toolchain builders.
https://luci-milo.appspot.com/ui/p/fuchsia/builders/toolchain.ci/clang-linux-x64/b8751656876289840849/overview
Commit: 0c6c016dbf6285de5ba4bf561eeb7669a9a4f87b
https://github.com/llvm/llvm-project/commit/0c6c016dbf6285de5ba4bf561eeb7669a9a4f87b
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-04-03 (Wed, 03 Apr 2024)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
A clang/test/CodeGen/arm-v8.2a-neon-intrinsics-generic.c
M clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c
M clang/test/CodeGen/pseudo-probe-emit.c
M clang/www/c_status.html
M flang/include/flang/Runtime/io-api.h
M flang/runtime/environment.cpp
M flang/runtime/environment.h
M flang/runtime/freestanding-tools.h
M flang/runtime/io-api.cpp
M flang/runtime/io-error.cpp
M flang/runtime/io-error.h
M flang/runtime/namelist.cpp
M libc/config/baremetal/api.td
M libc/config/gpu/api.td
M libc/config/linux/api.td
M libc/include/CMakeLists.txt
M libc/spec/posix.td
M libc/src/stdio/fseeko.h
M libc/src/stdio/ftello.h
M libcxx/docs/Status/Cxx23.rst
M libcxx/docs/Status/Cxx23Issues.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolLocator/CMakeLists.txt
M lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
A lldb/test/API/debuginfod/Normal/Makefile
A lldb/test/API/debuginfod/Normal/TestDebuginfod.py
A lldb/test/API/debuginfod/Normal/main.c
A lldb/test/API/debuginfod/SplitDWARF/Makefile
A lldb/test/API/debuginfod/SplitDWARF/TestDebuginfodDWP.py
A lldb/test/API/debuginfod/SplitDWARF/main.c
M llvm/include/llvm/ADT/iterator_range.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/Transforms/IPO/SampleProfileProbe.h
M llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/Target/AMDGPU/DSDIRInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrGISel.td
M llvm/lib/Transforms/IPO/SampleProfileProbe.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
M llvm/test/MC/AMDGPU/gfx1150_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3c_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3cx_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3c_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3cx_dpp8.txt
M llvm/test/MachineVerifier/test_g_fcmp.mir
M llvm/test/MachineVerifier/test_g_icmp.mir
M llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal-minmax.ll
A llvm/test/Transforms/SLPVectorizer/X86/icmp-altopcode-after-reordering.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-icmp-to-trunc.ll
M llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/scatter-vectorize-reorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/vec3-reorder-reshuffle.ll
M llvm/test/Transforms/SLPVectorizer/slp-umax-rdx-matcher-crash.ll
M llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile.prof
M llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-update.prof
M llvm/test/Transforms/SampleProfile/pseudo-probe-callee-profile-mismatch.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-discriminator.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-invoke.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-metadata-2.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-update.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-verify.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Support/Timing.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
Log Message:
-----------
fix ---
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/d36b525d4646...0c6c016dbf62
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