[all-commits] [llvm/llvm-project] 8aa3a7: [RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYE...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8aa3a77eaf198afb7e01453e6daf6566b687945d
      https://github.com/llvm/llvm-project/commit/8aa3a77eaf198afb7e01453e6daf6566b687945d
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-03 (Wed, 03 Apr 2024)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrGISel.td
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-anyext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-icmp.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-splatvector-s64-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-zext.mir
    M llvm/test/MachineVerifier/test_g_fcmp.mir
    M llvm/test/MachineVerifier/test_g_icmp.mir

  Log Message:
  -----------
  [RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

This patch legalizes G_ZEXT, G_SEXT, and G_ANYEXT. If the type is a
legal mask type, then the instruction is legalized as the element-wise
select, where the condition on the select is the mask typed source
operand, and the true and false values are 1 or -1 (for
zero/any-extension and sign extension) and zero. If the type is a legal integer
or vector integer type, then the instruction is marked as legal.

The legalization of the extends may introduce a G_SPLAT_VECTOR, which
needs to be legalized in this patch for the extend test cases to pass.

A G_SPLAT_VECTOR is legal if the vector type is a legal integer or
floating point vector type and the source operand is sXLen type. This is
because the SelectionDAG patterns only support sXLen typed
ISD::SPLAT_VECTORS, and we'd like to reuse those patterns. A
G_SPLAT_VECTOR is cutom legalized if it has a legal s1 element vector
type and s1 scalar operand. It is legalized to G_VMSET_VL or G_VMCLR_VL
if the splat is all ones or all zeros respectivley. In the case of a
non-constant mask splat, we legalize by promoting the scalar value to
s8.

In order to get the s8 element vector back into s1 vector, we use a
G_ICMP. In order for the splat vector and extend tests to pass, we also
need to legalize G_ICMP in this patch.

A G_ICMP is legal if the destination type is a legal bool vector and the LHS and
RHS are legal integer vector types.


  Commit: 05f673bcefb0912a38a67b0026cad3768b2f85d2
      https://github.com/llvm/llvm-project/commit/05f673bcefb0912a38a67b0026cad3768b2f85d2
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-03 (Wed, 03 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir

  Log Message:
  -----------
  [RISCV][GISEL] Regbank select for scalable vector G_ICMP


  Commit: 35a9393a3f775d4e1506965b9cfeedd45599f1a7
      https://github.com/llvm/llvm-project/commit/35a9393a3f775d4e1506965b9cfeedd45599f1a7
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-03 (Wed, 03 Apr 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir

  Log Message:
  -----------
  [RISCV][GISEL] Instruction selection for G_ICMP


  Commit: 188ca374ee601a50b6f5f6c1cf7e7dc3998e3a62
      https://github.com/llvm/llvm-project/commit/188ca374ee601a50b6f5f6c1cf7e7dc3998e3a62
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-03 (Wed, 03 Apr 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir

  Log Message:
  -----------
  [RISCV][GISEL] Regbankselect for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type


  Commit: 63c925ca808f216f805b76873743450456e350f2
      https://github.com/llvm/llvm-project/commit/63c925ca808f216f805b76873743450456e350f2
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-04-03 (Wed, 03 Apr 2024)

  Changed paths:
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir

  Log Message:
  -----------
  [RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with scalable vector type


Compare: https://github.com/llvm/llvm-project/compare/029e1d751503...63c925ca808f

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