[all-commits] [llvm/llvm-project] 439176: [MLIR][LLVM][Mem2Reg] Relax type equality requirem...

[Christian Ulmann via All-commits]

  Branch: refs/heads/users/dinistro/mem2reg-inconsistent-type-support
  Home:   https://github.com/llvm/llvm-project
  Commit: 43917624bf366850cb949725f83135ee0b4b055e
      https://github.com/llvm/llvm-project/commit/43917624bf366850cb949725f83135ee0b4b055e
  Author: Christian Ulmann <christian.ulmann at nextsilicon.com>
  Date:   2024-04-03 (Wed, 03 Apr 2024)

  Changed paths:
    M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/test/Dialect/LLVMIR/mem2reg.mlir

  Log Message:
  -----------
  [MLIR][LLVM][Mem2Reg] Relax type equality requirement for load and store

This commit relaxes Mem2Reg's type equality requirement for the LLVM
dialect's load and store operations. For now, we only allow loads to be
promoted if the reaching definition can be bitcasted into a value of the
target type.



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