[all-commits] [llvm/llvm-project] 2a315d: [RISCV] Combine (or disjoint ext, ext) -> vwadd (#...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2a315d800bb352fe459a012006a42ac7cd63834e
      https://github.com/llvm/llvm-project/commit/2a315d800bb352fe459a012006a42ac7cd63834e
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-29 (Fri, 29 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll

  Log Message:
  -----------
  [RISCV] Combine (or disjoint ext, ext) -> vwadd (#86929)

DAGCombiner (or InstCombine) will convert an add to an or if the bits
are disjoint, which can prevent what was originally an (add {s,z}ext,
{s,z}ext) from being selected as a vwadd.

This teaches combineBinOp_VLToVWBinOp_VL to recover it by treating it as
an add.



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