[all-commits] [llvm/llvm-project] a3c2d8: [RISCV] Combine ({s, u}{div, rem} (zext, zext)) -> (...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a3c2d8c0720424579c2a9b6313664908db7fcb14
      https://github.com/llvm/llvm-project/commit/a3c2d8c0720424579c2a9b6313664908db7fcb14
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-03-29 (Fri, 29 Mar 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/binop-zext.ll

  Log Message:
  -----------
  [RISCV] Combine ({s,u}{div,rem} (zext, zext)) -> (zext ({s,u}{div,rem} (zext, zext))) (#86779)

This narrows unsigned and signed div and rem nodes via
combineBinOpOfZExt.

Unlike other binary ops, there are no widening div or rem instructions.
So we will end up with an extra vzext.vf2.

However I'm assuming that div/rem are expensive enough that by reducing
their EMUL we will gain back the cost.

Alive2 proof: https://alive2.llvm.org/ce/z/Et_L6y



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