[all-commits] [llvm/llvm-project] 856e81: [DAGCombiner] Set disjoint flag in add->or and xor...
Luke Lau via All-commits
all-commits at lists.llvm.org
Thu Mar 28 03:09:21 PDT 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 856e815ca1c416de263438e90e8120947e33a03c
https://github.com/llvm/llvm-project/commit/856e815ca1c416de263438e90e8120947e33a03c
Author: Luke Lau <luke at igalia.com>
Date: 2024-03-28 (Thu, 28 Mar 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_isel.ll.expected
Log Message:
-----------
[DAGCombiner] Set disjoint flag in add->or and xor->or combines (#86925)
We check DAG.haveNoCommonBitsSet so the operands will be known to be
disjoint.
I couldn't think of a codegen test case since most targets aren't
checking hasDisjoint yet, apart from RISCV in the or_is_add pattern, but
it also falls back to computeKnownBits.
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