[all-commits] [llvm/llvm-project] 13b653: [clang][RISCV] Enable RVV with function attribute ...

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 13b653ab112736b92cd7f8ef249ced2b148ee7f4
      https://github.com/llvm/llvm-project/commit/13b653ab112736b92cd7f8ef249ced2b148ee7f4
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-03-27 (Wed, 27 Mar 2024)

  Changed paths:
    M clang/include/clang/Sema/Sema.h
    M clang/lib/Sema/Sema.cpp
    M clang/lib/Sema/SemaChecking.cpp
    M clang/lib/Sema/SemaDecl.cpp
    M clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
    M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
    M clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
    M clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb-error.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (#83674)

It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include <riscv_vector.h>

__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
  return __riscv_vadd(v1, v2, vl);
}

int other_add(int i1, int i2) {
  return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.



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